From: Pratyush Yadav <p.yadav@ti.com>
To: Boris Brezillon <boris.brezillon@collabora.com>
Cc: Alexandre Belloni <alexandre.belloni@bootlin.com>,
Mason Yang <masonccyang@mxic.com.tw>,
Vignesh Raghavendra <vigneshr@ti.com>,
Tudor Ambarus <tudor.ambarus@microchip.com>,
Richard Weinberger <richard@nod.at>, Sekhar Nori <nsekhar@ti.com>,
Nicolas Ferre <nicolas.ferre@microchip.com>,
linux-kernel@vger.kernel.org,
Ludovic Desroches <ludovic.desroches@microchip.com>,
Mark Brown <broonie@kernel.org>,
linux-mtd@lists.infradead.org,
Miquel Raynal <miquel.raynal@bootlin.com>,
Matthias Brugger <matthias.bgg@gmail.com>,
linux-mediatek@lists.infradead.org, linux-spi@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v6 04/19] spi: spi-mem: allow specifying a command's extension
Date: Fri, 22 May 2020 01:11:31 +0530 [thread overview]
Message-ID: <20200521194129.3lqdormmcs4zadh2@ti.com> (raw)
In-Reply-To: <20200521202256.5816eb32@collabora.com>
On 21/05/20 08:22PM, Boris Brezillon wrote:
> On Wed, 20 May 2020 22:00:38 +0530
> Pratyush Yadav <p.yadav@ti.com> wrote:
>
> > In xSPI mode, flashes expect 2-byte opcodes. The second byte is called
> > the "command extension". There can be 3 types of extensions in xSPI:
> > repeat, invert, and hex. When the extension type is "repeat", the same
> > opcode is sent twice. When it is "invert", the second byte is the
> > inverse of the opcode. When it is "hex" an additional opcode byte based
> > is sent with the command whose value can be anything.
> >
> > So, make opcode a 16-bit value and add a 'nbytes', similar to how
> > multiple address widths are handled.
> >
> > Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
> > ---
> > include/linux/spi/spi-mem.h | 5 ++++-
> > 1 file changed, 4 insertions(+), 1 deletion(-)
> >
> > diff --git a/include/linux/spi/spi-mem.h b/include/linux/spi/spi-mem.h
> > index e3dcb956bf61..731bb64c6ba6 100644
> > --- a/include/linux/spi/spi-mem.h
> > +++ b/include/linux/spi/spi-mem.h
> > @@ -69,6 +69,8 @@ enum spi_mem_data_dir {
> >
> > /**
> > * struct spi_mem_op - describes a SPI memory operation
> > + * @cmd.nbytes: number of opcode bytes (only 1 or 2 are valid). The opcode is
> > + * sent MSB-first.
> > * @cmd.buswidth: number of IO lines used to transmit the command
> > * @cmd.opcode: operation opcode
> > * @cmd.dtr: whether the command opcode should be sent in DTR mode or not
> > @@ -94,9 +96,10 @@ enum spi_mem_data_dir {
> > */
> > struct spi_mem_op {
> > struct {
> > + u8 nbytes;
> > u8 buswidth;
> > u8 dtr : 1;
> > - u8 opcode;
> > + u16 opcode;
> > } cmd;
> >
> > struct {
>
> As mentioned in one of my previous review, you should patch the mxic
> driver before extending the opcode field:
IIUC, this patchset doesn't break original functionality of the driver.
It will work like before with 1-byte opcodes. So I don't think it is the
responsibility of this patchset to enhance the driver. It didn't work
before with 2-byte opcodes, it won't work now. IMO this should be a
separate, independent change.
> --->8---
> diff --git a/drivers/spi/spi-mxic.c b/drivers/spi/spi-mxic.c
> index 69491f3a515d..c3f4136a7c1d 100644
> --- a/drivers/spi/spi-mxic.c
> +++ b/drivers/spi/spi-mxic.c
> @@ -356,6 +356,7 @@ static int mxic_spi_mem_exec_op(struct spi_mem *mem,
> int nio = 1, i, ret;
> u32 ss_ctrl;
> u8 addr[8];
> + u8 cmd[2];
>
> ret = mxic_spi_set_freq(mxic, mem->spi->max_speed_hz);
> if (ret)
> @@ -393,7 +394,10 @@ static int mxic_spi_mem_exec_op(struct spi_mem *mem,
> writel(readl(mxic->regs + HC_CFG) | HC_CFG_MAN_CS_ASSERT,
> mxic->regs + HC_CFG);
>
> - ret = mxic_spi_data_xfer(mxic, &op->cmd.opcode, NULL, 1);
> + for (i = 0; i < op->cmd.nbytes; i++)
> + cmd[i] = op->cmd.opcode >> (8 * (op->cmd.nbytes - i - 1));
> +
> + ret = mxic_spi_data_xfer(mxic, cmd, NULL, op->cmd.nbytes);
> if (ret)
> goto out;
>
--
Regards,
Pratyush Yadav
Texas Instruments India
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next prev parent reply other threads:[~2020-05-21 19:41 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-20 16:30 [PATCH v6 00/19] mtd: spi-nor: add xSPI Octal DTR support Pratyush Yadav
2020-05-20 16:30 ` [PATCH v6 01/19] spi: spi-mem: allow specifying whether an op is DTR or not Pratyush Yadav
2020-05-20 16:30 ` [PATCH v6 02/19] spi: atmel-quadspi: reject DTR ops Pratyush Yadav
2020-05-20 16:30 ` [PATCH v6 03/19] spi: spi-mtk-nor: " Pratyush Yadav
2020-05-20 16:30 ` [PATCH v6 04/19] spi: spi-mem: allow specifying a command's extension Pratyush Yadav
2020-05-21 18:22 ` Boris Brezillon
2020-05-21 19:41 ` Pratyush Yadav [this message]
2020-05-21 20:03 ` Pratyush Yadav
2020-05-21 20:16 ` Boris Brezillon
2020-05-22 18:23 ` Pratyush Yadav
2020-05-20 16:30 ` [PATCH v6 05/19] mtd: spi-nor: add support for DTR protocol Pratyush Yadav
2020-05-20 16:30 ` [PATCH v6 06/19] mtd: spi-nor: sfdp: default to addr_width of 3 for configurable widths Pratyush Yadav
2020-05-20 16:30 ` [PATCH v6 07/19] mtd: spi-nor: sfdp: prepare BFPT parsing for JESD216 rev D Pratyush Yadav
2020-05-20 16:30 ` [PATCH v6 08/19] mtd: spi-nor: sfdp: get command opcode extension type from BFPT Pratyush Yadav
2020-05-20 16:30 ` [PATCH v6 09/19] mtd: spi-nor: sfdp: parse xSPI Profile 1.0 table Pratyush Yadav
2020-05-20 16:30 ` [PATCH v6 10/19] mtd: spi-nor: core: use dummy cycle and address width info from SFDP Pratyush Yadav
2020-05-20 16:30 ` [PATCH v6 11/19] mtd: spi-nor: core: do 2 byte reads for SR and FSR in DTR mode Pratyush Yadav
2020-05-20 16:30 ` [PATCH v6 12/19] mtd: spi-nor: core: enable octal DTR mode when possible Pratyush Yadav
2020-05-20 16:30 ` [PATCH v6 13/19] mtd: spi-nor: sfdp: do not make invalid quad enable fatal Pratyush Yadav
2020-05-20 16:30 ` [PATCH v6 14/19] mtd: spi-nor: sfdp: detect Soft Reset sequence support from BFPT Pratyush Yadav
2020-05-20 16:30 ` [PATCH v6 15/19] mtd: spi-nor: core: perform a Soft Reset on shutdown Pratyush Yadav
2020-05-20 16:30 ` [PATCH v6 16/19] mtd: spi-nor: core: disable Octal DTR mode on suspend Pratyush Yadav
2020-05-20 16:30 ` [PATCH v6 17/19] mtd: spi-nor: core: expose spi_nor_default_setup() in core.h Pratyush Yadav
2020-05-20 16:30 ` [PATCH v6 18/19] mtd: spi-nor: spansion: add support for Cypress Semper flash Pratyush Yadav
2020-05-20 16:30 ` [PATCH v6 19/19] mtd: spi-nor: micron-st: allow using MT35XU512ABA in Octal DTR mode Pratyush Yadav
2020-05-21 16:39 ` [PATCH v6 00/19] mtd: spi-nor: add xSPI Octal DTR support Mark Brown
2020-05-21 18:05 ` Pratyush Yadav
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