From: Miquel Raynal <miquel.raynal@bootlin.com>
To: Md Sadre Alam <mdalam@codeaurora.org>
Cc: devicetree@vger.kernel.org, vigneshr@ti.com, richard@nod.at,
linux-kernel@vger.kernel.org, robh+dt@kernel.org,
bjorn.andersson@linaro.org, agross@kernel.org,
linux-mtd@lists.infradead.org, linux-arm-msm@vger.kernel.org,
sricharan@codeaurora.org
Subject: Re: [PATCH 0/5] mtd: rawnand: qcom: Add support for QSPI nand
Date: Wed, 28 Oct 2020 10:48:35 +0100 [thread overview]
Message-ID: <20201028104835.3dc31745@xps13> (raw)
In-Reply-To: <1602307902-16761-1-git-send-email-mdalam@codeaurora.org>
Hello,
Md Sadre Alam <mdalam@codeaurora.org> wrote on Sat, 10 Oct 2020
11:01:37 +0530:
> QPIC 2.0 supports Serial NAND support in addition to all features and
> commands in QPIC 1.0 for parallel NAND. Parallel and Serial NAND cannot
> operate simultaneously. QSPI nand devices will connect to QPIC IO_MACRO
> block of QPIC controller. There is a separate IO_MACRO clock for IO_MACRO
> block. Default IO_MACRO block divide the input clock by 4. so if IO_MACRO
> input clock is 320MHz then on bus it will be 80MHz, so QSPI nand device
> should also support this frequency.
>
> QPIC provides 4 data pins to QSPI nand. In standard SPI mode (x1 mode) data
> transfer will occur on only 2 pins one pin for Serial data in and one for
> serial data out. In QUAD SPI mode (x4 mode) data transfer will occur at all
> the four data lines. QPIC controller supports command for x1 mode and x4 mode.
>
> Md Sadre Alam (5):
> dt-bindings: qcom_nandc: IPQ5018 QPIC NAND documentation
> mtd: rawnand: qcom: Add initial support for qspi nand
> mtd: rawnand: qcom: Read QPIC version
> mtd: rawnand: qcom: Enable support for erase,read & write for serial
> nand.
> mtd: rawnand: qcom: Add support for serial training.
>
> .../devicetree/bindings/mtd/qcom_nandc.txt | 3 +
> drivers/mtd/nand/raw/nand_ids.c | 13 +
> drivers/mtd/nand/raw/qcom_nandc.c | 502 ++++++++++++++++++++-
> 3 files changed, 494 insertions(+), 24 deletions(-)
>
I'm sorry but this series clearly breaks the current layering. I cannot
authorize SPI-NAND code to fall into the raw NAND subsystem.
As both typologies cannot be used at the same time, I guess you should
have another driver handling this feature under the spi/ subsystem +
a few declarations in the SPI-NAND devices list.
Thanks,
Miquèl
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next prev parent reply other threads:[~2020-10-28 9:49 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-10 5:31 [PATCH 0/5] mtd: rawnand: qcom: Add support for QSPI nand Md Sadre Alam
2020-10-10 5:31 ` [PATCH 1/5] dt-bindings: qcom_nandc: IPQ5018 QPIC NAND documentation Md Sadre Alam
2020-10-13 16:21 ` Rob Herring
2020-10-10 5:31 ` [PATCH 2/5] mtd: rawnand: qcom: Add initial support for qspi nand Md Sadre Alam
2020-10-29 9:07 ` Boris Brezillon
2023-03-06 14:15 ` Md Sadre Alam
2023-03-06 14:33 ` Md Sadre Alam
2023-03-06 14:38 ` Miquel Raynal
2023-03-27 13:54 ` Md Sadre Alam
2023-03-27 14:49 ` Miquel Raynal
2023-03-28 11:18 ` Md Sadre Alam
2020-10-10 5:31 ` [PATCH 3/5] mtd: rawnand: qcom: Read QPIC version Md Sadre Alam
2020-10-10 5:31 ` [PATCH 4/5] mtd: rawnand: qcom: Enable support for erase, read & write for serial nand Md Sadre Alam
2020-10-10 5:31 ` [PATCH 5/5] mtd: rawnand: qcom: Add support for serial training Md Sadre Alam
2020-10-28 9:48 ` Miquel Raynal [this message]
2020-10-28 18:24 ` [PATCH 0/5] mtd: rawnand: qcom: Add support for QSPI nand mdalam
2020-10-29 7:53 ` Miquel Raynal
2020-10-29 8:37 ` Miquel Raynal
2020-10-29 8:38 ` Boris Brezillon
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