From: Michael Walle <michael@walle.cc>
To: Jungseung Lee <js07.lee@samsung.com>
Cc: Vignesh Raghavendra <vigneshr@ti.com>,
chenxiang <chenxiang66@hisilicon.com>,
John Garry <john.garry@huawei.com>,
linux-mtd@lists.infradead.org,
Tudor Ambarus <tudor.ambarus@microchip.com>,
js07.lee@gmail.com
Subject: Re: [PATCH v2 2/3] mtd: spi-nor: add 4bit block protection support
Date: Sat, 21 Mar 2020 21:47:33 +0100 [thread overview]
Message-ID: <268fed929cc4c5d9b1c3711f9f19d559@walle.cc> (raw)
In-Reply-To: <20200318120615.4639-2-js07.lee@samsung.com>
Hi Jungseung,
Am 2020-03-18 13:06, schrieb Jungseung Lee:
> Currently, we are supporting block protection only for flash chips with
> 3 block protection bits in the SR register.
>
> This patch enables block protection support for flashes with 4 block
> protection bits(bp0-3).
>
> Added a flag to inform that this flash has 4 block protection bit,
> and added another flag for some flashes in which bp3 bit is not
> adjacent
> to other bp bits.
>
> Signed-off-by: Jungseung Lee <js07.lee@samsung.com>
Please add a changelog if you're doing a new patch version. This will
greatly ease the review.
> ---
> drivers/mtd/spi-nor/core.c | 62 ++++++++++++++++++++++++++++++++++---
> drivers/mtd/spi-nor/core.h | 10 ++++++
> include/linux/mtd/spi-nor.h | 2 ++
> 3 files changed, 69 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
> index e4ed8553aae8..842e2fabdb20 100644
> --- a/drivers/mtd/spi-nor/core.c
> +++ b/drivers/mtd/spi-nor/core.c
> @@ -1516,7 +1516,15 @@ static int spi_nor_erase(struct mtd_info *mtd,
> struct erase_info *instr)
>
> static u8 spi_nor_get_bp_mask(struct spi_nor *nor)
> {
> - return SR_BP2 | SR_BP1 | SR_BP0;
> + u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
> +
> + if (nor->flags & SNOR_F_HAS_SR_BP3_BIT6)
> + return mask | SR_BP3_BIT6;
> +
> + if (nor->flags & SNOR_F_HAS_4BIT_BP)
> + return mask | SR_BP3;
> +
> + return mask;
> }
>
> static u8 spi_nor_get_tb_mask(struct spi_nor *nor)
> @@ -1532,7 +1540,8 @@ static int spi_nor_get_min_prot_length(struct
> spi_nor *nor)
> int bp_slots, bp_slots_needed;
> u8 mask = spi_nor_get_bp_mask(nor);
>
> - bp_slots = (mask >> SR_BP_SHIFT) + 1;
> + /* 2 ^ number_of_bp_bit slots available */
> + bp_slots = 1 << hweight8(mask);
>
> /* Reserved one for "protect none" and one for "protect all". */
> bp_slots = bp_slots - 2;
> @@ -1553,7 +1562,12 @@ static void spi_nor_get_locked_range_sr(struct
> spi_nor *nor, u8 sr, loff_t *ofs,
> int min_prot_len;
> u8 mask = spi_nor_get_bp_mask(nor);
> u8 tb_mask = spi_nor_get_tb_mask(nor);
> - u8 bp = (sr & mask) >> SR_BP_SHIFT;
> + u8 bp, val = sr & mask;
> +
you could add a comment here. It is not obvious why one don't need
to check nor->flags & SNOR_F_HAS_SR_BP3_BIT6. Ie. it is already
masked with mask retrieved from spi_nor_get_bp_mask() which makes
sure the SR_BP3_BIT6 may only be set if nor->flags contains that
specific flag. Or just be explicit and do
if (nor->flags & SNOR_F_HAS_SR_BP3_BIT6 && val & SR_BP3_BIT6)
I'd prefer the latter because
(1) its the same as you've done it below
(2) its easier to understand in the future
That being said. Nice work! So if you do a respin with that you
can add:
Reviewed-by: Michael Walle <michael@walle.cc>
Tested with a MX25U3232F (no upstream support yet).
Tested-by: Michael Walle <michael@walle.cc>
> + if (val & SR_BP3_BIT6)
> + val = (val & ~SR_BP3_BIT6) | SR_BP3;
> +
> + bp = val >> SR_BP_SHIFT;
>
> if (!bp) {
> /* No protection */
> @@ -1611,7 +1625,7 @@ static int spi_nor_is_unlocked_sr(struct spi_nor
> *nor, loff_t ofs, uint64_t len,
>
> /*
> * Lock a region of the flash. Compatible with ST Micro and similar
> flash.
> - * Supports the block protection bits BP{0,1,2} in the status register
> + * Supports the block protection bits BP{0,1,2}/BP{0,1,2,3} in the
> status register
> * (SR). Does not support these features found in newer SR bitfields:
> * - SEC: sector/block protect - only handle SEC=0 (block protect)
> * - CMP: complement protect - only support CMP=0 (range is not
> complemented)
> @@ -1619,7 +1633,7 @@ static int spi_nor_is_unlocked_sr(struct spi_nor
> *nor, loff_t ofs, uint64_t len,
> * Support for the following is provided conditionally for some flash:
> * - TB: top/bottom protect
> *
> - * Sample table portion for 8MB flash (Winbond w25q64fw):
> + * Sample table portion for 8MB flash (Winbond w25q64fw / BP0-2):
> *
> * SEC | TB | BP2 | BP1 | BP0 | Prot Length | Protected
> Portion
> *
> --------------------------------------------------------------------------
> @@ -1639,6 +1653,32 @@ static int spi_nor_is_unlocked_sr(struct
> spi_nor *nor, loff_t ofs, uint64_t len,
> * 0 | 1 | 1 | 0 | 1 | 2 MB | Lower 1/4
> * 0 | 1 | 1 | 1 | 0 | 4 MB | Lower 1/2
> *
> + * Sample table portion for 64MB flash (Micron n25q512ax3 / BP0-3):
> + *
> + * TB | BP3 | BP2 | BP1 | BP0 | Prot Length | Protected
> Portion
> + *
> --------------------------------------------------------------------------
> + * 0 | 0 | 0 | 0 | 0 | NONE | NONE
> + * 0 | 0 | 0 | 0 | 1 | 64 KB | Upper
> 1/1024
> + * 0 | 0 | 0 | 1 | 0 | 128 KB | Upper
> 1/512
> + * 0 | 0 | 0 | 1 | 1 | 256 KB | Upper
> 1/256
> + * ...
> + * 0 | 1 | 0 | 0 | 1 | 16 MB | Upper 1/4
> + * 0 | 1 | 0 | 1 | 0 | 32 MB | Upper 1/2
> + * 0 | 1 | 0 | 1 | 1 | 64 MB | ALL
> + * 0 | 1 | 1 | 0 | 0 | 64 MB | ALL
> + * ...
> + *
> ------|-------|-------|-------|-------|---------------|-------------------
> + * 1 | 0 | 0 | 0 | 0 | NONE | NONE
> + * 1 | 0 | 0 | 0 | 1 | 64 KB | Lower
> 1/1024
> + * 1 | 0 | 0 | 1 | 0 | 128 KB | Lower
> 1/512
> + * 1 | 0 | 0 | 1 | 1 | 256 KB | Lower
> 1/256
> + * ...
> + * 1 | 1 | 0 | 0 | 1 | 16 MB | Lower 1/4
> + * 1 | 1 | 0 | 1 | 0 | 32 MB | Lower 1/2
> + * 1 | 1 | 0 | 1 | 1 | 64 MB | ALL
> + * 1 | 1 | 1 | 0 | 0 | 64 MB | ALL
> + * ...
> + *
> * Returns negative on errors, 0 on success.
> */
> static int spi_nor_sr_lock(struct spi_nor *nor, loff_t ofs, uint64_t
> len)
> @@ -1690,6 +1730,9 @@ static int spi_nor_sr_lock(struct spi_nor *nor,
> loff_t ofs, uint64_t len)
> min_prot_len = spi_nor_get_min_prot_length(nor);
> pow = ilog2(lock_len) - ilog2(min_prot_len) + 1;
> val = pow << SR_BP_SHIFT;
> +
> + if (nor->flags & SNOR_F_HAS_SR_BP3_BIT6 && val & SR_BP3)
> + val = (val & ~SR_BP3) | SR_BP3_BIT6;
> }
>
> if (val & ~mask)
> @@ -1772,6 +1815,9 @@ static int spi_nor_sr_unlock(struct spi_nor
> *nor, loff_t ofs, uint64_t len)
> pow = ilog2(lock_len) - ilog2(min_prot_len) + 1;
> val = pow << SR_BP_SHIFT;
>
> + if (nor->flags & SNOR_F_HAS_SR_BP3_BIT6 && val & SR_BP3)
> + val = (val & ~SR_BP3) | SR_BP3_BIT6;
> +
> /* Some power-of-two sizes are not supported */
> if (val & ~mask)
> return -EINVAL;
> @@ -3131,6 +3177,12 @@ int spi_nor_scan(struct spi_nor *nor, const char
> *name,
> if (info->flags & USE_CLSR)
> nor->flags |= SNOR_F_USE_CLSR;
>
> + if (info->flags & SPI_NOR_4BIT_BP) {
> + nor->flags |= SNOR_F_HAS_4BIT_BP;
> + if (info->flags & SPI_NOR_BP3_SR_BIT6)
> + nor->flags |= SNOR_F_HAS_SR_BP3_BIT6;
> + }
> +
> if (info->flags & SPI_NOR_NO_ERASE)
> mtd->flags |= MTD_NO_ERASE;
>
> diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h
> index 3ce826b35ad1..6f2f6b27173f 100644
> --- a/drivers/mtd/spi-nor/core.h
> +++ b/drivers/mtd/spi-nor/core.h
> @@ -24,6 +24,8 @@ enum spi_nor_option_flags {
> SNOR_F_HAS_16BIT_SR = BIT(9),
> SNOR_F_NO_READ_CR = BIT(10),
> SNOR_F_HAS_SR_TB_BIT6 = BIT(11),
> + SNOR_F_HAS_4BIT_BP = BIT(12),
> + SNOR_F_HAS_SR_BP3_BIT6 = BIT(13),
> };
>
> struct spi_nor_read_command {
> @@ -301,6 +303,14 @@ struct flash_info {
> * status register. Must be used with
> * SPI_NOR_HAS_TB.
> */
> +#define SPI_NOR_4BIT_BP BIT(17) /*
> + * Flash SR has 4 bit fields (BP0-3)
> + * for block protection.
> + */
> +#define SPI_NOR_BP3_SR_BIT6 BIT(18) /*
> + * BP3 is bit 6 of status register.
> + * Must be used with SPI_NOR_4BIT_BP.
> + */
>
> /* Part specific fixup hooks. */
> const struct spi_nor_fixups *fixups;
> diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
> index e656858b50a5..1e2af0ec1f03 100644
> --- a/include/linux/mtd/spi-nor.h
> +++ b/include/linux/mtd/spi-nor.h
> @@ -111,7 +111,9 @@
> #define SR_BP0 BIT(2) /* Block protect 0 */
> #define SR_BP1 BIT(3) /* Block protect 1 */
> #define SR_BP2 BIT(4) /* Block protect 2 */
> +#define SR_BP3 BIT(5) /* Block protect 3 */
> #define SR_TB_BIT5 BIT(5) /* Top/Bottom protect */
> +#define SR_BP3_BIT6 BIT(6) /* Block protect 3 */
> #define SR_TB_BIT6 BIT(6) /* Top/Bottom protect */
> #define SR_SRWD BIT(7) /* SR write protect */
> /* Spansion/Cypress specific status bits */
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next prev parent reply other threads:[~2020-03-21 20:48 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <CGME20200318120801epcas1p3845986eadf5f4aea47233f71e4e60508@epcas1p3.samsung.com>
2020-03-18 12:06 ` [PATCH v2 1/3] mtd: spi-nor: reimplement block protection handling Jungseung Lee
[not found] ` <CGME20200318120803epcas1p34570b795db84b2fd429b299a9ab317bd@epcas1p3.samsung.com>
2020-03-18 12:06 ` [PATCH v2 2/3] mtd: spi-nor: add 4bit block protection support Jungseung Lee
2020-03-21 20:47 ` Michael Walle [this message]
[not found] ` <CGME20200318120804epcas1p37b89db641c44ac84a778447bc6d7fbf2@epcas1p3.samsung.com>
2020-03-18 12:06 ` [PATCH v2 3/3] mtd: spi-nor: support lock/unlock for a few Micron chips Jungseung Lee
2020-03-21 20:48 ` [PATCH v2 1/3] mtd: spi-nor: reimplement block protection handling Michael Walle
2020-01-13 5:37 [PATCH v2 1/3] mtd: spi-nor: introduce SR_BP_SHIFT define Jungseung Lee
[not found] ` <CGME20200113053757epcas1p1815715938095590a8bb8342eeb1e9012@epcas1p1.samsung.com>
2020-01-13 5:37 ` [PATCH v2 2/3] mtd: spi-nor: add 4bit block protection support Jungseung Lee
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