From: <Tudor.Ambarus@microchip.com>
To: <michael@walle.cc>
Cc: vigneshr@ti.com, richard@nod.at, linux-kernel@vger.kernel.org,
boris.brezillon@collabora.com, linux-mtd@lists.infradead.org,
miquel.raynal@bootlin.com
Subject: Re: [PATCH v5 3/3] mtd: spi-nor: keep lock bits if they are non-volatile
Date: Thu, 26 Nov 2020 16:47:36 +0000 [thread overview]
Message-ID: <897d0205-b4c1-b5a7-6034-d0d7144c0868@microchip.com> (raw)
In-Reply-To: <f6344b9cb5c61c3bfd075e231b708269@walle.cc>
On 11/25/20 8:52 PM, Michael Walle wrote:
>> Looks like BP3 is needed here.
>
> https://ww1.microchip.com/downloads/en/DeviceDoc/20005036C.pdf
>
> agreed. But again cannot test it. Would add it as a seperate patch
> to this series. (or leave it like it is)
Separate patch for the TB/BP3 bits is fine. We should add a fixes tag
for the patch that introduced the bug:
commit 3e0930f109e76 ("mtd: spi-nor: Rework the disabling of block write protection")
cheers,
ta
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next prev parent reply other threads:[~2020-11-26 16:48 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-03 15:32 [PATCH v5 0/3] mtd: spi-nor: keep lock bits if they are non-volatile Michael Walle
2020-10-03 15:32 ` [PATCH v5 1/3] mtd: spi-nor: atmel: remove global protection flag Michael Walle
2020-11-24 19:09 ` Tudor.Ambarus
2020-11-25 18:17 ` Michael Walle
2020-11-26 12:45 ` Tudor.Ambarus
2020-11-26 12:59 ` Tudor.Ambarus
2020-11-26 16:42 ` Tudor.Ambarus
2020-11-26 18:44 ` Michael Walle
2020-10-03 15:32 ` [PATCH v5 2/3] mtd: spi-nor: sst: " Michael Walle
2020-11-24 19:50 ` Tudor.Ambarus
2020-10-03 15:32 ` [PATCH v5 3/3] mtd: spi-nor: keep lock bits if they are non-volatile Michael Walle
2020-11-25 12:21 ` Tudor.Ambarus
2020-11-25 18:52 ` Michael Walle
2020-11-26 16:47 ` Tudor.Ambarus [this message]
2020-11-26 20:46 ` Michael Walle
2020-10-27 22:26 ` [PATCH v5 0/3] " Michael Walle
2020-11-10 13:07 ` Vignesh Raghavendra
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