From: masonccyang@mxic.com.tw
To: "Vignesh Raghavendra" <vigneshr@ti.com>
Cc: devicetree@vger.kernel.org, Vignesh Raghavendra <vigneshr@ti.com>,
Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>,
Boris Brezillon <bbrezillon@kernel.org>,
Richard Weinberger <richard@nod.at>,
linux-kernel@vger.kernel.org, Marek Vasut <marek.vasut@gmail.com>,
Rob Herring <robh+dt@kernel.org>,
linux-mtd@lists.infradead.org,
Miquel Raynal <miquel.raynal@bootlin.com>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v7 3/5] mtd: Add support for HyperBus memory devices
Date: Wed, 26 Jun 2019 09:16:29 +0800 [thread overview]
Message-ID: <OF97D41CEB.1200A9E4-ON48258425.0006AA42-48258425.000700E5@mxic.com.tw> (raw)
In-Reply-To: <20190620172250.9102-4-vigneshr@ti.com>
Hi Vignesh,
>
> Subject
>
> [PATCH v7 3/5] mtd: Add support for HyperBus memory devices
>
> Cypress' HyperBus is Low Signal Count, High Performance Double Data Rate
> Bus interface between a host system master and one or more slave
> interfaces. HyperBus is used to connect microprocessor, microcontroller,
> or ASIC devices with random access NOR flash memory (called HyperFlash)
> or self refresh DRAM (called HyperRAM).
>
> Its a 8-bit data bus (DQ[7:0]) with Read-Write Data Strobe (RWDS)
> signal and either Single-ended clock(3.0V parts) or Differential clock
> (1.8V parts). It uses ChipSelect lines to select b/w multiple slaves.
> At bus level, it follows a separate protocol described in HyperBus
> specification[1].
>
> HyperFlash follows CFI AMD/Fujitsu Extended Command Set (0x0002) similar
> to that of existing parallel NORs. Since HyperBus is x8 DDR bus,
> its equivalent to x16 parallel NOR flash wrt bits per clock cycle. But
> HyperBus operates at >166MHz frequencies.
> HyperRAM provides direct random read/write access to flash memory
> array.
>
> But, HyperBus memory controllers seem to abstract implementation details
> and expose a simple MMIO interface to access connected flash.
>
> Add support for registering HyperFlash devices with MTD framework. MTD
> maps framework along with CFI chip support framework are used to support
> communicating with flash.
>
> Framework is modelled along the lines of spi-nor framework. HyperBus
> memory controller (HBMC) drivers calls hyperbus_register_device() to
> register a single HyperFlash device. HyperFlash core parses MMIO access
> information from DT, sets up the map_info struct, probes CFI flash and
> registers it with MTD framework.
>
> Some HBMC masters need calibration/training sequence[3] to be carried
> out, in order for DLL inside the controller to lock, by reading a known
> string/pattern. This is done by repeatedly reading CFI Query
> Identification String. Calibration needs to be done before trying to
detect
> flash as part of CFI flash probe.
>
> HyperRAM is not supported at the moment.
>
> HyperBus specification can be found at[1]
> HyperFlash datasheet can be found at[2]
>
> [1] https://www.cypress.com/file/213356/download
> [2] https://www.cypress.com/file/213346/download
> [3] http://www.ti.com/lit/ug/spruid7b/spruid7b.pdf
> Table 12-5741. HyperFlash Access Sequence
>
> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Cypress has announced the inclusion of Cypress’ high-bandwidth
HyperBus™ 8-bit serial memory interface into the new eXpanded SPI (xSPI)
electrical interface standard from the JEDEC Solid State Technology
Association
for detail, please goes to
https://www.cypress.com/news/cypress-hyperbus-memory-interface-instant-applications-incorporated-jedec-xspi-electrical
FYI,
thanks & best regards,
Mason
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next prev parent reply other threads:[~2019-06-26 1:17 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-20 17:22 [PATCH v7 0/5] MTD: Add Initial HyperBus support Vignesh Raghavendra
2019-06-20 17:22 ` [PATCH v7 1/5] mtd: cfi_cmdset_0002: Add support for polling status register Vignesh Raghavendra
2019-06-24 16:46 ` Tokunori Ikegami
2019-06-25 5:52 ` Vignesh Raghavendra
2019-06-20 17:22 ` [PATCH v7 2/5] dt-bindings: mtd: Add binding documentation for HyperFlash Vignesh Raghavendra
2019-06-20 17:22 ` [PATCH v7 3/5] mtd: Add support for HyperBus memory devices Vignesh Raghavendra
2019-06-21 19:52 ` Sergei Shtylyov
2019-06-24 13:33 ` Vignesh Raghavendra
2019-06-26 1:16 ` masonccyang [this message]
2019-06-26 6:00 ` Vignesh Raghavendra
2019-06-20 17:22 ` [PATCH v7 4/5] dt-bindings: mtd: Add bindings for TI's AM654 HyperBus memory controller Vignesh Raghavendra
2019-06-20 19:48 ` Sergei Shtylyov
2019-06-20 17:22 ` [PATCH v7 5/5] mtd: hyperbus: Add driver for TI's " Vignesh Raghavendra
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