From: <Tudor.Ambarus@microchip.com>
To: <tkuw584924@gmail.com>, <linux-mtd@lists.infradead.org>
Cc: <miquel.raynal@bootlin.com>, <richard@nod.at>, <vigneshr@ti.com>,
<p.yadav@ti.com>, <Bacem.Daassi@infineon.com>,
<Takahiro.Kuwano@infineon.com>
Subject: Re: [PATCH v4 6/6] mtd: spi-nor: spansion: Add s25hl-t/s25hs-t IDs and fixups
Date: Thu, 8 Apr 2021 10:03:59 +0000 [thread overview]
Message-ID: <ec9d4e56-8ace-f55d-a999-54a553b903ed@microchip.com> (raw)
In-Reply-To: <bcd8e956-c00e-df74-62ea-9cb746ae24eb@gmail.com>
On 4/8/21 11:21 AM, Takahiro Kuwano wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> Hi Tudor,
>
> On 4/8/2021 2:06 PM, Tudor.Ambarus@microchip.com wrote:
>> Hi,
>>
>> On 3/19/21 8:58 AM, tkuw584924@gmail.com wrote:
>>> +static int
>>> +s25hx_t_post_bfpt_fixups(struct spi_nor *nor,
>>> + const struct sfdp_parameter_header *bfpt_header,
>>> + const struct sfdp_bfpt *bfpt,
>>> + struct spi_nor_flash_parameter *params)
>>> +{
>>> + int ret;
>>> + u32 addr;
>>> + u8 cfr3v;
>>> +
>>> + ret = spi_nor_set_4byte_addr_mode(nor, true);
>>> + if (ret)
>>> + return ret;
>>> + nor->addr_width = 4;
>>
>> Takahiro, you are bypassing the core functions. spansion_set_4byte_addr_mode()
>> will be called at set_4byte_addr_mode() time, resulting in an illegal op?
>>
> Since the spansion_post_sfdp_fixups() adds the SNOR_F_4B_OPCODES flag,
> spansion_set_4byte_addr_mode() is not called actually.
right. Do we have to undo this somewhere, i.e, call
spi_nor_set_4byte_addr_mode(nor, false); ?
>
>> Are we safe to modify the core and do the spi_nor_set_addr_width() and
>> nor->params->set_4byte_addr_mode() before parsing SFDP?
>>
> It sounds not safe to me as there are some discussions about addr_width.
oh, yes, of course, because addr width and 4byte addr mode opcodes are
discovered when parsing SFDP. I need to drink my coffee before writing
emails :D.
>
> https://patchwork.ozlabs.org/project/linux-mtd/patch/20201212115817.5122-1-vigneshr@ti.com/
> https://patchwork.ozlabs.org/project/linux-mtd/patch/1611740450-47975-2-git-send-email-yangyicong@hisilicon.com/
>
> Best Regards,
> Takahiro
>
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next prev parent reply other threads:[~2021-04-08 10:05 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-19 6:51 [PATCH v4 0/6] mtd: spi-nor: Add support for Cypress s25hl-t/s25hs-t tkuw584924
2021-03-19 6:53 ` [PATCH v4 1/6] mtd: spi-nor: core: Add the ->ready() hook tkuw584924
2021-03-19 6:54 ` [PATCH v4 2/6] mtd: spi-nor: core: Expose spi_nor_clear_sr() to manufacturer drivers tkuw584924
2021-03-19 6:56 ` [PATCH v4 3/6] mtd: spi-nor: spansion: Add support for Read/Write Any Register tkuw584924
2021-03-22 9:36 ` Pratyush Yadav
2021-04-20 5:48 ` Takahiro Kuwano
2021-03-19 6:57 ` [PATCH v4 4/6] mtd: spi-nor: spansion: Add support for volatile QE bit tkuw584924
2021-03-19 6:58 ` [PATCH v4 5/6] mtd: spi-nor: spansion: Add status check for multi-die parts tkuw584924
2021-03-19 6:58 ` [PATCH v4 6/6] mtd: spi-nor: spansion: Add s25hl-t/s25hs-t IDs and fixups tkuw584924
2021-04-08 5:06 ` Tudor.Ambarus
2021-04-08 8:21 ` Takahiro Kuwano
2021-04-08 10:03 ` Tudor.Ambarus [this message]
2021-04-09 2:05 ` Takahiro Kuwano
2021-04-09 2:37 ` Tudor.Ambarus
2021-04-09 3:24 ` Takahiro Kuwano
2021-04-01 6:09 ` [PATCH v4 0/6] mtd: spi-nor: Add support for Cypress s25hl-t/s25hs-t Tudor.Ambarus
2021-04-02 7:13 ` Takahiro Kuwano
2021-04-08 5:35 ` Tudor.Ambarus
2021-04-09 8:50 ` Takahiro Kuwano
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