From: Catalin Marinas <catalin.marinas@arm.com>
To: "Suzuki K. Poulose" <Suzuki.Poulose@arm.com>
Cc: Stephen Rothwell <sfr@canb.auug.org.au>,
Thomas Gleixner <tglx@linutronix.de>, Ingo Molnar <mingo@elte.hu>,
"H. Peter Anvin" <hpa@zytor.com>,
Peter Zijlstra <peterz@infradead.org>,
linux-next@vger.kernel.org, linux-kernel@vger.kernel.org,
Marc Zyngier <marc.zyngier@arm.com>
Subject: Re: linux-next: manual merge of the tip tree with the arm64 tree
Date: Thu, 22 Oct 2015 16:32:01 +0100 [thread overview]
Message-ID: <20151022153201.GD26603@e104818-lin.cambridge.arm.com> (raw)
In-Reply-To: <20151022120602.GB28575@e106634-lin.cambridge.arm.com>
On Thu, Oct 22, 2015 at 01:06:03PM +0100, Suzuki K. Poulose wrote:
> On Thu, Oct 22, 2015 at 01:26:52PM +1100, Stephen Rothwell wrote:
> > Today's linux-next merge of the tip tree got a conflict in:
> >
> > arch/arm64/kernel/cpufeature.c
> >
> > between commit:
> >
> > da8d02d19ffd ("arm64/capabilities: Make use of system wide safe value")
> >
> > from the arm64 tree and commit:
> >
> > 963fcd409587 ("arm64: cpufeatures: Check ICC_EL1_SRE.SRE before enabling ARM64_HAS_SYSREG_GIC_CPUIF")
> >
> > from the tip tree.
> >
> > I fixed it up (I have no idea here, so I just used the arm64 tree version)
> > and can carry the fix as necessary (no action is required).
>
> We need the following patch applied to fix the conflict correctly
> on top of the -next tree.
Or, if it's easier, the combined diff resolution for the conflicting
code:
--------8<----------------------------
diff --cc arch/arm64/kernel/cpufeature.c
index d0d607452e1d,305f30dc9e63..ec552cf9e12d
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
[...]
+ static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry)
+ {
+ bool has_sre;
+
- if (!has_id_aa64pfr0_feature(entry))
++ if (!has_cpuid_feature(entry))
+ return false;
+
+ has_sre = gic_enable_sre();
+ if (!has_sre)
+ pr_warn_once("%s present but disabled by higher exception level\n",
+ entry->desc);
+
+ return has_sre;
+ }
+
static const struct arm64_cpu_capabilities arm64_features[] = {
{
.desc = "GIC system register CPU interface",
.capability = ARM64_HAS_SYSREG_GIC_CPUIF,
- .matches = has_cpuid_feature,
+ .matches = has_useable_gicv3_cpuif,
- .field_pos = 24,
+ .sys_reg = SYS_ID_AA64PFR0_EL1,
+ .field_pos = ID_AA64PFR0_GIC_SHIFT,
.min_field_value = 1,
},
#ifdef CONFIG_ARM64_PAN
--------8<----------------------------
Thanks.
--
Catalin
next prev parent reply other threads:[~2015-10-22 15:32 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-10-22 2:26 linux-next: manual merge of the tip tree with the arm64 tree Stephen Rothwell
2015-10-22 12:06 ` Suzuki K. Poulose
2015-10-22 15:32 ` Catalin Marinas [this message]
2015-10-31 22:17 ` Stephen Rothwell
-- strict thread matches above, loose matches on Subject: below --
2021-12-13 16:45 broonie
2021-08-27 4:09 Stephen Rothwell
2020-05-22 6:11 Stephen Rothwell
2020-03-18 4:27 Stephen Rothwell
2020-03-18 8:50 ` Catalin Marinas
2020-03-10 1:49 Stephen Rothwell
2019-04-15 4:25 Stephen Rothwell
2019-04-15 4:21 Stephen Rothwell
2017-11-01 5:47 Stephen Rothwell
2017-11-13 22:52 ` Stephen Rothwell
2017-08-22 3:38 Stephen Rothwell
2017-09-04 5:29 ` Stephen Rothwell
2017-06-16 3:25 Stephen Rothwell
2017-07-03 1:29 ` Stephen Rothwell
2017-03-31 3:02 Stephen Rothwell
2017-03-31 9:32 ` Arnd Bergmann
2017-03-31 11:24 ` Stephen Rothwell
2016-09-12 2:54 Stephen Rothwell
2016-05-12 2:00 Stephen Rothwell
2016-04-29 3:56 Stephen Rothwell
2016-04-29 9:04 ` Matt Fleming
2016-02-26 1:53 Stephen Rothwell
2016-02-26 1:53 Stephen Rothwell
2015-10-15 3:05 Stephen Rothwell
2015-10-13 2:10 Stephen Rothwell
2015-10-13 9:50 ` Will Deacon
2014-05-23 6:44 Stephen Rothwell
2014-05-23 9:23 ` Catalin Marinas
2014-05-23 6:28 Stephen Rothwell
2014-05-23 8:41 ` Catalin Marinas
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