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From: "Aneesh Kumar K.V" <aneesh.kumar@linux.ibm.com>
To: linuxppc-dev@lists.ozlabs.org, mpe@ellerman.id.au,
	linux-nvdimm@lists.01.org, dan.j.williams@intel.com
Cc: Jan Kara <jack@suse.cz>,
	msuchanek@suse.de,
	"Aneesh Kumar K.V" <aneesh.kumar@linux.ibm.com>
Subject: [PATCH v7 2/7] powerpc/pmem: Add new instructions for persistent storage and sync
Date: Wed,  1 Jul 2020 12:52:30 +0530	[thread overview]
Message-ID: <20200701072235.223558-3-aneesh.kumar@linux.ibm.com> (raw)
In-Reply-To: <20200701072235.223558-1-aneesh.kumar@linux.ibm.com>

POWER10 introduces two new variants of dcbf instructions (dcbstps and dcbfps)
that can be used to write modified locations back to persistent storage.

Additionally, POWER10 also introduce phwsync and plwsync which can be used
to establish order of these writes to persistent storage.

This patch exposes these instructions to the rest of the kernel. The existing
dcbf and hwsync instructions in P8 and P9 are adequate to enable appropriate
synchronization with OpenCAPI-hosted persistent storage. Hence the new
instructions are added as a variant of the old ones that old hardware
won't differentiate.

Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com>
---
 arch/powerpc/include/asm/ppc-opcode.h | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h
index 2a39c716c343..1ad014e4633e 100644
--- a/arch/powerpc/include/asm/ppc-opcode.h
+++ b/arch/powerpc/include/asm/ppc-opcode.h
@@ -219,6 +219,8 @@
 #define PPC_INST_STWCX			0x7c00012d
 #define PPC_INST_LWSYNC			0x7c2004ac
 #define PPC_INST_SYNC			0x7c0004ac
+#define PPC_INST_PHWSYNC		0x7c8004ac
+#define PPC_INST_PLWSYNC		0x7ca004ac
 #define PPC_INST_SYNC_MASK		0xfc0007fe
 #define PPC_INST_ISYNC			0x4c00012c
 #define PPC_INST_LXVD2X			0x7c000698
@@ -284,6 +286,8 @@
 #define PPC_INST_TABORT			0x7c00071d
 #define PPC_INST_TSR			0x7c0005dd
 
+#define PPC_INST_DCBF			0x7c0000ac
+
 #define PPC_INST_NAP			0x4c000364
 #define PPC_INST_SLEEP			0x4c0003a4
 #define PPC_INST_WINKLE			0x4c0003e4
@@ -532,6 +536,14 @@
 #define STBCIX(s,a,b)		stringify_in_c(.long PPC_INST_STBCIX | \
 				       __PPC_RS(s) | __PPC_RA(a) | __PPC_RB(b))
 
+#define	PPC_DCBFPS(a, b)	stringify_in_c(.long PPC_INST_DCBF |	\
+				       ___PPC_RA(a) | ___PPC_RB(b) | (4 << 21))
+#define	PPC_DCBSTPS(a, b)	stringify_in_c(.long PPC_INST_DCBF |	\
+				       ___PPC_RA(a) | ___PPC_RB(b) | (6 << 21))
+
+#define	PPC_PHWSYNC		stringify_in_c(.long PPC_INST_PHWSYNC)
+#define	PPC_PLWSYNC		stringify_in_c(.long PPC_INST_PLWSYNC)
+
 /*
  * Define what the VSX XX1 form instructions will look like, then add
  * the 128 bit load store instructions based on that.
-- 
2.26.2
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  parent reply	other threads:[~2020-07-01  7:23 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-07-01  7:22 [PATCH v7 0/7] Support new pmem flush and sync instructions for POWER Aneesh Kumar K.V
2020-07-01  7:22 ` [PATCH v7 1/7] powerpc/pmem: Restrict papr_scm to P8 and above Aneesh Kumar K.V
2020-07-01  7:22 ` Aneesh Kumar K.V [this message]
2020-07-01  7:22 ` [PATCH v7 3/7] powerpc/pmem: Add flush routines using new pmem store and sync instruction Aneesh Kumar K.V
2020-07-01  7:22 ` [PATCH v7 4/7] libnvdimm/nvdimm/flush: Allow architecture to override the flush barrier Aneesh Kumar K.V
2020-07-01  7:22 ` [PATCH v7 5/7] powerpc/pmem: Update ppc64 to use the new barrier instruction Aneesh Kumar K.V
2020-07-01  7:22 ` [PATCH v7 6/7] powerpc/pmem: Avoid the barrier in flush routines Aneesh Kumar K.V
2020-07-01  7:22 ` [PATCH v7 7/7] powerpc/pmem: Initialize pmem device on newer hardware Aneesh Kumar K.V
2020-07-16 12:55 ` [PATCH v7 0/7] Support new pmem flush and sync instructions for POWER Michael Ellerman

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