From: Jon Hunter <jonathanh@nvidia.com>
To: Jisheng Zhang <Jisheng.Zhang@synaptics.com>,
Kishon Vijay Abraham I <kishon@ti.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Rob Herring <robh@kernel.org>,
Bjorn Helgaas <bhelgaas@google.com>,
Jingoo Han <jingoohan1@gmail.com>, Kukjin Kim <kgene@kernel.org>,
Krzysztof Kozlowski <krzk@kernel.org>,
Richard Zhu <hongxing.zhu@nxp.com>,
Lucas Stach <l.stach@pengutronix.de>,
Shawn Guo <shawnguo@kernel.org>,
Sascha Hauer <s.hauer@pengutronix.de>,
Pengutronix Kernel Team <kernel@pengutronix.de>,
Fabio Estevam <festevam@gmail.com>,
NXP Linux Team <linux-imx@nxp.com>,
"Yue Wang" <yue.wang@Amlogic.com>,
Kevin Hilman <khilman@baylibre.com>,
"Neil Armstrong" <narmstrong@baylibre.com>,
Jerome Brunet <jbrunet@baylibre.com>,
Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
Jesper Nilsson <jesper.nilsson@axis.com>,
Gustavo Pimentel <gustavo.pimentel@synopsys.com>,
Xiaowei Song <songxiaowei@hisilicon.com>,
Binghui Wang <wangbinghui@hisilicon.com>,
Andy Gross <agross@kernel.org>,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Stanimir Varbanov <svarbanov@mm-sol.com>,
Pratyush Anand <pratyush.anand@gmail.com>,
Thierry Reding <thierry.reding@gmail.com>,
Kunihiko Hayashi <hayashi.kunihiko@socionext.com>,
Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: <linux-omap@vger.kernel.org>, <linux-pci@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>,
<linux-samsung-soc@vger.kernel.org>,
<linux-amlogic@lists.infradead.org>, <linux-arm-kernel@axis.com>,
<linux-arm-msm@vger.kernel.org>, <linux-tegra@vger.kernel.org>,
Vidya Sagar <vidyas@nvidia.com>
Subject: Re: [PATCH v2 0/5] PCI: dwc: improve msi handling
Date: Fri, 25 Sep 2020 09:53:45 +0100 [thread overview]
Message-ID: <de4d9294-4f6d-c7d1-efc7-c8ef6570bd64@nvidia.com> (raw)
In-Reply-To: <20200924190421.549cb8fc@xhacker.debian>
On 24/09/2020 12:05, Jisheng Zhang wrote:
> Improve the msi code:
> 1. Add proper error handling.
> 2. Move dw_pcie_msi_init() from each users to designware host to solve
> msi page leakage in resume path.
Apologies if this is slightly off topic, but I have been meaning to ask
about MSIs and PCI. On Tegra194 which uses the DWC PCI driver, whenever we
hotplug CPUs we see the following warnings ...
[ 79.068351] WARNING KERN IRQ70: set affinity failed(-22).
[ 79.068362] WARNING KERN IRQ71: set affinity failed(-22).
These interrupts are the MSIs ...
70: 0 0 0 0 0 0 0 0 PCI-MSI 134217728 Edge PCIe PME, aerdrv
71: 0 0 0 0 0 0 0 0 PCI-MSI 134742016 Edge ahci[0001:01:00.0]
This caused because ...
static int dw_pci_msi_set_affinity(struct irq_data *d,
const struct cpumask *mask, bool force)
{
return -EINVAL;
}
Now the above is not unique to the DWC PCI host driver, it appears that
most PCIe drivers also do the same. However, I am curious if there is
any way to avoid the above warnings given that setting the affinity does
not appear to be supported in anyway AFAICT.
Cheers
Jon
--
nvpublic
next prev parent reply other threads:[~2020-09-25 8:54 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-24 11:05 [PATCH v2 0/5] PCI: dwc: improve msi handling Jisheng Zhang
2020-09-24 11:05 ` [PATCH v2 1/5] PCI: dwc: Call dma_unmap_page() before freeing the msi page Jisheng Zhang
2020-09-24 11:48 ` Gustavo Pimentel
2020-09-24 11:06 ` [PATCH v2 2/5] PCI: dwc: Check alloc_page() return value Jisheng Zhang
2020-09-24 11:47 ` Gustavo Pimentel
2020-09-29 17:29 ` Marc Zyngier
2020-09-30 1:23 ` Jisheng Zhang
2020-09-24 11:06 ` [PATCH v2 3/5] PCI: dwc: Rename dw_pcie_free_msi to dw_pcie_msi_deinit Jisheng Zhang
2020-09-24 11:49 ` Gustavo Pimentel
2020-09-24 11:07 ` [PATCH v2 4/5] PCI: dwc: Skip PCIE_MSI_INTR0* programming if MSI is disabled Jisheng Zhang
2020-09-24 11:49 ` Gustavo Pimentel
2020-09-24 11:07 ` [PATCH v2 5/5] PCI: dwc: Move dw_pcie_msi_init() from each users to designware host Jisheng Zhang
2020-10-08 5:43 ` Vidya Sagar
2021-03-07 22:10 ` Krzysztof Wilczyński
2021-03-11 6:50 ` Jisheng Zhang
2020-09-25 8:53 ` Jon Hunter [this message]
2020-09-25 9:17 ` [PATCH v2 0/5] PCI: dwc: improve msi handling Jisheng Zhang
2020-09-25 9:27 ` Jisheng Zhang
2020-09-25 15:13 ` Jon Hunter
2020-09-27 8:28 ` Jisheng Zhang
2020-09-28 17:46 ` Jon Hunter
2020-09-29 10:48 ` Jisheng Zhang
2020-09-29 13:22 ` Jon Hunter
2020-09-29 17:25 ` Marc Zyngier
2020-09-29 18:02 ` Jon Hunter
2020-09-29 18:12 ` Marc Zyngier
2020-10-06 6:26 ` Vidya Sagar
2020-10-06 6:36 ` Jisheng Zhang
2020-10-08 5:32 ` Vidya Sagar
2020-10-09 8:37 ` [PATCH] PCI: dwc: Move dw_pcie_msi_init() from each users to designware host Jisheng Zhang
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