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From: Alan Douglas <adouglas@cadence.com>
To: <lorenzo.pieralisi@arm.com>
Cc: <kishon@ti.com>, <bhelgaas@google.com>,
	<linux-pci@vger.kernel.org>, <gustavo.pimentel@synopsys.com>,
	<cyrille.pitchen@bootlin.com>,
	Alan Douglas <adouglas@cadence.com>
Subject: [PATCH v4 3/4] PCI: cadence: Check whether MSI is masked before sending it
Date: Thu, 11 Oct 2018 17:16:11 +0100	[thread overview]
Message-ID: <1539274571-545-1-git-send-email-adouglas@cadence.com> (raw)

The EP driver did not check the mask bit for each MSI before
sending it in raise_irq.  This is now checked, and -EINVAL is
returned if masked.

Fixes: 37dddf14f1ae ("PCI: cadence: Add EndPoint Controller driver for Cadence PCIe controller")
Signed-off-by: Alan Douglas <adouglas@cadence.com>
---
 drivers/pci/controller/pcie-cadence-ep.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/pci/controller/pcie-cadence-ep.c b/drivers/pci/controller/pcie-cadence-ep.c
index c3a0889..b762214 100644
--- a/drivers/pci/controller/pcie-cadence-ep.c
+++ b/drivers/pci/controller/pcie-cadence-ep.c
@@ -332,6 +332,11 @@ static int cdns_pcie_ep_send_msi_irq(struct cdns_pcie_ep *ep, u8 fn,
 	if (!interrupt_num || interrupt_num > msi_count)
 		return -EINVAL;
 
+	/* Check whether MSI is masked */
+	data = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_MASK_64);
+	if (data & (1 << (interrupt_num - 1)))
+		return -EINVAL;
+
 	/* Compute the data value to be written. */
 	data_mask = msi_count - 1;
 	data = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_DATA_64);
-- 
1.9.0


             reply	other threads:[~2018-10-11 16:16 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-10-11 16:16 Alan Douglas [this message]
2018-10-16 16:01 ` [PATCH v4 3/4] PCI: cadence: Check whether MSI is masked before sending it Lorenzo Pieralisi
2018-10-17  9:50   ` Alan Douglas

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