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From: Yicong Yang <yangyicong@hisilicon.com>
To: <helgaas@kernel.org>, <linux-pci@vger.kernel.org>
Cc: <f.fangjian@huawei.com>
Subject: [PATCH 5/6] PCI: Add PCIE_LNKCAP2_SLS2SPEED macro
Date: Wed, 15 Jan 2020 17:04:22 +0800	[thread overview]
Message-ID: <1579079063-5668-6-git-send-email-yangyicong@hisilicon.com> (raw)
In-Reply-To: <1579079063-5668-1-git-send-email-yangyicong@hisilicon.com>

Add PCIE_LNKCAP2_SLS2SPEED macro for transforming raw link cap 2
value to link speed. Use it in pcie_get_speed_cap() to reduce
redundancy. We'll not touch the functions when new link
speed comes.

Signed-off-by: Yicong Yang <yangyicong@hisilicon.com>
---
 drivers/pci/pci.c | 17 ++++-------------
 drivers/pci/pci.h |  9 +++++++++
 2 files changed, 13 insertions(+), 13 deletions(-)

diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index dce32ce..2ef4030 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -5780,19 +5780,10 @@ enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev)
 	 * where only 2.5 GT/s and 5.0 GT/s speeds were defined.
 	 */
 	pcie_capability_read_dword(dev, PCI_EXP_LNKCAP2, &lnkcap2);
-	if (lnkcap2) { /* PCIe r3.0-compliant */
-		if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_32_0GB)
-			return PCIE_SPEED_32_0GT;
-		else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB)
-			return PCIE_SPEED_16_0GT;
-		else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB)
-			return PCIE_SPEED_8_0GT;
-		else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB)
-			return PCIE_SPEED_5_0GT;
-		else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB)
-			return PCIE_SPEED_2_5GT;
-		return PCI_SPEED_UNKNOWN;
-	}
+
+	/* PCIe r3.0-compliant */
+	if (lnkcap2)
+		return PCIE_LNKCAP2_SLS2SPEED(lnkcap2);
 
 	pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap);
 	if ((lnkcap & PCI_EXP_LNKCAP_SLS) == PCI_EXP_LNKCAP_SLS_5_0GB)
diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
index 5e1f810..3d988e9 100644
--- a/drivers/pci/pci.h
+++ b/drivers/pci/pci.h
@@ -290,6 +290,15 @@ void pci_disable_bridge_window(struct pci_dev *dev);
 struct pci_bus *pci_bus_get(struct pci_bus *bus);
 void pci_bus_put(struct pci_bus *bus);
 
+/* PCIe link information from Link Capabilities 2 */
+#define PCIE_LNKCAP2_SLS2SPEED(lnkcap2) \
+	((lnkcap2) & PCI_EXP_LNKCAP2_SLS_32_0GB ? PCIE_SPEED_32_0GT : \
+	 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_16_0GB ? PCIE_SPEED_16_0GT : \
+	 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_8_0GB ? PCIE_SPEED_8_0GT : \
+	 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_5_0GB ? PCIE_SPEED_5_0GT : \
+	 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_2_5GB ? PCIE_SPEED_2_5GT : \
+	 PCI_SPEED_UNKNOWN)
+
 /* PCIe link information */
 #define PCI_SPEED2STR(speed) \
 	((speed) == PCI_SPEED_UNKNOWN ? "Unknown speed" : \
-- 
2.8.1


  parent reply	other threads:[~2020-01-15  9:08 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-01-15  9:04 [PATCH 0/6] Improve link speed presentation process Yicong Yang
2020-01-15  9:04 ` [PATCH 1/6] PCI: add 32 GT/s decoding in some macros Yicong Yang
2020-01-15  9:04 ` [PATCH 2/6] PCI: Make pci_bus_speed_strings[] public Yicong Yang
2020-02-05 18:35   ` Bjorn Helgaas
2020-02-06  1:47     ` Yicong Yang
2020-01-15  9:04 ` [PATCH 3/6] PCI: Add comments for link speed info arrays Yicong Yang
2020-01-15  9:04 ` [PATCH 4/6] PCI: Improve and rename PCIE_SPEED2STR macro Yicong Yang
2020-02-05 18:50   ` Bjorn Helgaas
2020-02-06  1:50     ` Yicong Yang
2020-01-15  9:04 ` Yicong Yang [this message]
2020-02-05 18:54   ` [PATCH 5/6] PCI: Add PCIE_LNKCAP2_SLS2SPEED macro Bjorn Helgaas
2020-02-06  1:53     ` Yicong Yang
2020-01-15  9:04 ` [PATCH 6/6] PCI: Reduce redundancy in current_link_speed_show() Yicong Yang
2020-02-05  9:37 ` [PATCH 0/6] Improve link speed presentation process Yicong Yang

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