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From: Rob Herring <robh@kernel.org>
To: Kishon Vijay Abraham I <kishon@ti.com>
Cc: Gustavo Pimentel <gustavo.pimentel@synopsys.com>,
	Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
	Jingoo Han <jingoohan1@gmail.com>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Mark Rutland <mark.rutland@arm.com>,
	Arnd Bergmann <arnd@arndb.de>,
	Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	Murali Karicheri <m-karicheri2@ti.com>,
	Jesper Nilsson <jesper.nilsson@axis.com>,
	linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org, linux-arm-kernel@axis.com
Subject: Re: [PATCH 09/24] dt-bindings: PCI: Document "atu" reg-names
Date: Mon, 21 Jan 2019 18:48:06 -0600	[thread overview]
Message-ID: <20190122004806.GA32204@bogus> (raw)
In-Reply-To: <20190114132424.6445-10-kishon@ti.com>

On Mon, Jan 14, 2019 at 06:54:09PM +0530, Kishon Vijay Abraham I wrote:
> Document "atu" reg-names required to get the register space for ATU in
> Synopsys designware core version >= 4.80.
> 
> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> ---
>  Documentation/devicetree/bindings/pci/designware-pcie.txt | 7 +++++--
>  1 file changed, 5 insertions(+), 2 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt b/Documentation/devicetree/bindings/pci/designware-pcie.txt
> index c124f9bc11f3..5561a1c060d0 100644
> --- a/Documentation/devicetree/bindings/pci/designware-pcie.txt
> +++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt
> @@ -4,8 +4,11 @@ Required properties:
>  - compatible:
>  	"snps,dw-pcie" for RC mode;
>  	"snps,dw-pcie-ep" for EP mode;
> -- reg: Should contain the configuration address space.
> -- reg-names: Must be "config" for the PCIe configuration space.
> +- reg: For designware cores version < 4.80 contains the configuration
> +       address space. For designware core version >= 4.80, contains
> +       the configuration and ATU address space
> +- reg-names: Must be "config" for the PCIe configuration space and "atu" for
> +	     the ATU address space.

I'm pretty sure we already have other platforms with an ATU. Those all 
just represent it with the other ctrl registers? So maybe this is TI 
specific that it is separate. Or should have some conditional like 'if 
the ATU space is separate, the reg-name should be atu'.

>      (The old way of getting the configuration address space from "ranges"
>      is deprecated and should be avoided.)
>  - num-lanes: number of lanes to use
> -- 
> 2.17.1
> 

  reply	other threads:[~2019-01-22  0:48 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-01-14 13:24 [PATCH 00/24] Add support for PCIe RC and EP mode in TI's AM654 SoC Kishon Vijay Abraham I
2019-01-14 13:24 ` [PATCH 01/24] PCI: keystone: Add start_link/stop_link dw_pcie_ops Kishon Vijay Abraham I
2019-01-14 13:24 ` [PATCH 02/24] PCI: keystone: Cleanup error_irq configuration Kishon Vijay Abraham I
2019-01-14 13:24 ` [PATCH 03/24] dt-bindings: PCI: keystone: Add "reg-names" binding information Kishon Vijay Abraham I
2019-01-22  0:31   ` Rob Herring
2019-01-14 13:24 ` [PATCH 04/24] PCI: keystone: Perform host initialization in a single function Kishon Vijay Abraham I
2019-01-14 13:24 ` [PATCH 05/24] PCI: keystone: Use platform_get_resource_byname to get memory resources Kishon Vijay Abraham I
2019-01-14 13:24 ` [PATCH 06/24] PCI: keystone: Move initializations to appropriate places Kishon Vijay Abraham I
2019-01-14 13:24 ` [PATCH 07/24] dt-bindings: PCI: Add dt-binding to configure PCIe mode Kishon Vijay Abraham I
2019-01-22  0:32   ` Rob Herring
2019-01-14 13:24 ` [PATCH 08/24] PCI: keystone: Explicitly set the " Kishon Vijay Abraham I
2019-01-14 13:24 ` [PATCH 09/24] dt-bindings: PCI: Document "atu" reg-names Kishon Vijay Abraham I
2019-01-22  0:48   ` Rob Herring [this message]
2019-01-23 10:04     ` Kishon Vijay Abraham I
2019-01-14 13:24 ` [PATCH 10/24] PCI: dwc: Enable iATU unroll for endpoint too Kishon Vijay Abraham I
2019-01-14 13:24 ` [PATCH 11/24] PCI: dwc: Fix ATU identification for designware version >= 4.80 Kishon Vijay Abraham I
2019-01-14 13:24 ` [PATCH 12/24] PCI: keystone: Prevent ARM32 specific code to be compiled for ARM64 Kishon Vijay Abraham I
2019-01-14 13:24 ` [PATCH 13/24] dt-bindings: PCI: Add PCI RC dt binding documentation for AM654 Kishon Vijay Abraham I
2019-01-22  0:48   ` Rob Herring
2019-01-14 13:24 ` [PATCH 14/24] PCI: keystone: Add support for PCIe RC in AM654x Platforms Kishon Vijay Abraham I
2019-01-14 13:24 ` [PATCH 15/24] PCI: keystone: Invoke phy_reset API before enabling PHY Kishon Vijay Abraham I
2019-01-14 13:24 ` [PATCH 16/24] PCI: endpoint: Add support to allocate aligned buffers to be mapped in BARs Kishon Vijay Abraham I
2019-01-14 13:24 ` [PATCH 17/24] PCI: dwc: Add const qualifier to struct dw_pcie_ep_ops Kishon Vijay Abraham I
2019-01-14 13:24 ` [PATCH 18/24] PCI: dwc: Fix dw_pcie_ep_find_capability to return correct capability offset Kishon Vijay Abraham I
2019-01-29  9:25   ` Gustavo Pimentel
2019-01-29 10:19     ` Kishon Vijay Abraham I
2019-01-14 13:24 ` [PATCH 19/24] PCI: dwc: Add callbacks for accessing dbi2 address space Kishon Vijay Abraham I
2019-01-14 13:24 ` [PATCH 20/24] PCI: keystone: Add support for PCIe EP in AM654x Platforms Kishon Vijay Abraham I
2019-01-14 13:24 ` [PATCH 21/24] PCI: designware-ep: Configure RESBAR to advertise the smallest size Kishon Vijay Abraham I
2019-01-14 13:24 ` [PATCH 22/24] PCI: designware-ep: Use aligned ATU window for raising MSI interrupts Kishon Vijay Abraham I
2019-01-14 13:24 ` [PATCH 23/24] misc: pci_endpoint_test: Add support to test PCI EP in AM654x Kishon Vijay Abraham I
2019-01-14 13:24 ` [PATCH 24/24] misc: pci_endpoint_test: Fix test_reg_bar to be updated in pci_endpoint_test Kishon Vijay Abraham I
2019-02-04 16:40 ` [PATCH 00/24] Add support for PCIe RC and EP mode in TI's AM654 SoC Lorenzo Pieralisi
2019-02-06 12:50   ` Kishon Vijay Abraham I

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