From: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
To: Stefan Agner <stefan@agner.ch>
Cc: jingoohan1@gmail.com, gustavo.pimentel@synopsys.com,
l.stach@pengutronix.de, tpiepho@impinj.com,
leonard.crestez@nxp.com, bhelgaas@google.com,
linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 1/2] PCI: dwc: allow to limit registers set length
Date: Fri, 8 Feb 2019 11:10:58 +0000 [thread overview]
Message-ID: <20190208111058.GC13009@e107981-ln.cambridge.arm.com> (raw)
In-Reply-To: <14fafdf52d19feb9c926c312f4e3ba7ff8a4bad9.1549446867.git.stefan@agner.ch>
On Wed, Feb 06, 2019 at 10:57:31AM +0100, Stefan Agner wrote:
> Add length to the struct dw_pcie and check that the accessors
> dw_pcie_(rd|wr)_conf() do not read/write beyond that point.
>
> Suggested-by: Trent Piepho <tpiepho@impinj.com>
> Signed-off-by: Stefan Agner <stefan@agner.ch>
> ---
> Changes in v4:
> - Move length check to dw_pcie_rd_conf
> Changes in v5:
> - Rebased ontop of pci/dwc
>
> .../pci/controller/dwc/pcie-designware-host.c | 16 ++++++++++++++--
> drivers/pci/controller/dwc/pcie-designware.h | 1 +
> 2 files changed, 15 insertions(+), 2 deletions(-)
Applied to pci/dwc for v5.1, thanks.
Lorenzo
PS: Remember adding a version number to the patches next time please,
thanks.
> diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
> index 45ff5e4f8af6..bad54204fb52 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-host.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-host.c
> @@ -612,14 +612,20 @@ static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
> int size, u32 *val)
> {
> struct pcie_port *pp = bus->sysdata;
> + struct dw_pcie *pci;
>
> if (!dw_pcie_valid_device(pp, bus, PCI_SLOT(devfn))) {
> *val = 0xffffffff;
> return PCIBIOS_DEVICE_NOT_FOUND;
> }
>
> - if (bus->number == pp->root_bus_nr)
> + if (bus->number == pp->root_bus_nr) {
> + pci = to_dw_pcie_from_pp(pp);
> + if (pci->dbi_length && where + size > pci->dbi_length)
> + return PCIBIOS_BAD_REGISTER_NUMBER;
> +
> return dw_pcie_rd_own_conf(pp, where, size, val);
> + }
>
> return dw_pcie_rd_other_conf(pp, bus, devfn, where, size, val);
> }
> @@ -628,12 +634,18 @@ static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
> int where, int size, u32 val)
> {
> struct pcie_port *pp = bus->sysdata;
> + struct dw_pcie *pci;
>
> if (!dw_pcie_valid_device(pp, bus, PCI_SLOT(devfn)))
> return PCIBIOS_DEVICE_NOT_FOUND;
>
> - if (bus->number == pp->root_bus_nr)
> + if (bus->number == pp->root_bus_nr) {
> + pci = to_dw_pcie_from_pp(pp);
> + if (pci->dbi_length && where + size > pci->dbi_length)
> + return PCIBIOS_BAD_REGISTER_NUMBER;
> +
> return dw_pcie_wr_own_conf(pp, where, size, val);
> + }
>
> return dw_pcie_wr_other_conf(pp, bus, devfn, where, size, val);
> }
> diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> index 279000255ad1..d1d95119a422 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.h
> +++ b/drivers/pci/controller/dwc/pcie-designware.h
> @@ -226,6 +226,7 @@ struct dw_pcie_ops {
> struct dw_pcie {
> struct device *dev;
> void __iomem *dbi_base;
> + int dbi_length;
> void __iomem *dbi_base2;
> /* Used when iatu_unroll_enabled is true */
> void __iomem *atu_base;
> --
> 2.20.1
>
next prev parent reply other threads:[~2019-02-08 11:11 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-02-06 9:57 [PATCH 1/2] PCI: dwc: allow to limit registers set length Stefan Agner
2019-02-06 9:57 ` [PATCH 2/2] PCI: imx6: limit DBI register length Stefan Agner
2019-02-11 21:39 ` Bjorn Helgaas
2019-02-12 8:54 ` Lucas Stach
2019-02-12 11:33 ` Lorenzo Pieralisi
2019-02-12 19:07 ` Stefan Agner
2019-02-06 18:02 ` [PATCH 1/2] PCI: dwc: allow to limit registers set length Lorenzo Pieralisi
2019-02-07 15:08 ` [PATCH 1/2] Acked-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com> Gustavo Pimentel
2019-02-08 11:10 ` Lorenzo Pieralisi [this message]
-- strict thread matches above, loose matches on Subject: below --
2018-11-19 9:41 [PATCH 1/2] PCI: dwc: allow to limit registers set length Stefan Agner
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