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Hou" To: "linux-pci@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "bhelgaas@google.com" , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "l.subrahmanya@mobiveil.co.in" , "shawnguo@kernel.org" , Leo Li , "lorenzo.pieralisi@arm.com" , "catalin.marinas@arm.com" , "will.deacon@arm.com" CC: Mingkai Hu , "M.h. Lian" , Xiaowei Bao , "Z.q. Hou" Subject: [PATCHv4 25/28] PCI: mobiveil: ls_pcie_g4: add Workaround for A-011577 Thread-Topic: [PATCHv4 25/28] PCI: mobiveil: ls_pcie_g4: add Workaround for A-011577 Thread-Index: AQHU1+14+TCeS3tabUCUvLQeJSezBA== Date: Mon, 11 Mar 2019 09:33:23 +0000 Message-ID: <20190311093130.7209-26-Zhiqiang.Hou@nxp.com> References: <20190311093130.7209-1-Zhiqiang.Hou@nxp.com> In-Reply-To: <20190311093130.7209-1-Zhiqiang.Hou@nxp.com> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: HK0PR03CA0015.apcprd03.prod.outlook.com (2603:1096:203:2e::27) To AM6PR04MB5781.eurprd04.prod.outlook.com (2603:10a6:20b:ad::19) authentication-results: spf=none (sender IP is ) smtp.mailfrom=zhiqiang.hou@nxp.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.17.1 x-originating-ip: [119.31.174.73] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: d4743724-3a80-421c-aa65-08d6a6049ad7 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0;PCL:0;RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600127)(711020)(4605104)(4618075)(2017052603328)(7153060)(7193020);SRVR:AM6PR04MB6150; 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received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: aeikiPdgOrm2uWNn3xczUhMbvEU83A0IRuN0DVmjjQgo8NJ0fGHOztTc8HWj67tTXW0zXU1FKpOe/+y3JO4lWHd/n7OoP5X9Q5yphcUyspwR4EOlqPMfoS48JXFHIpRxNrQMZ6hAW5m4GDxirmx0h1Xlhtw7iTP+EHOOY4iFU86QNq63j5FkhoSbFcXAflbvkaJROLSa6evrwTMwhdAOSoyngo1Ip5AypkqCDPowPAHs8AdII0d0RqLf5YDbkj+h2KGNZ9z6ka6KuAZBwtzOd0U5BmCYo0vcWWC5QaoG6jtYGUyprGwKsosVjBYXG+jCJNmf6RShCpUWYCz1uUuJ8ad+VbN0Klanhy3/BxI+3Uw+Nwna7JvfGhzZDP5jYMaZUe3vCZcfEhntq/aUHbkkkXWFYqEK/WvigNYj4AeKd5I= Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: d4743724-3a80-421c-aa65-08d6a6049ad7 X-MS-Exchange-CrossTenant-originalarrivaltime: 11 Mar 2019 09:33:23.0541 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR04MB6150 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Hou Zhiqiang PCIe configuration access to non-existent function triggered SERROR interrupt exception. Workaround: Disable error reporting on AXI bus during the Vendor ID read transactions in enumeration. This ERRATA is only for LX2160A Rev1.0, and it will be fixed in Rev2.0. Signed-off-by: Hou Zhiqiang --- V4: - no change .../controller/mobiveil/pci-layerscape-gen4.c | 37 +++++++++++++++++++ .../controller/mobiveil/pcie-mobiveil-host.c | 17 ++++++++- .../pci/controller/mobiveil/pcie-mobiveil.h | 3 ++ 3 files changed, 56 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/mobiveil/pci-layerscape-gen4.c b/driver= s/pci/controller/mobiveil/pci-layerscape-gen4.c index 174cbcac4059..d2c5dbbd5e3c 100644 --- a/drivers/pci/controller/mobiveil/pci-layerscape-gen4.c +++ b/drivers/pci/controller/mobiveil/pci-layerscape-gen4.c @@ -22,8 +22,13 @@ =20 #include "pcie-mobiveil.h" =20 +#define REV_1_0 (0x10) + /* LUT and PF control registers */ #define PCIE_LUT_OFF (0x80000) +#define PCIE_LUT_GCR (0x28) +#define PCIE_LUT_GCR_RRE (0) + #define PCIE_PF_OFF (0xc0000) #define PCIE_PF_INT_STAT (0x18) #define PF_INT_STAT_PABRST (31) @@ -41,6 +46,7 @@ struct ls_pcie_g4 { struct mobiveil_pcie *pci; struct delayed_work dwork; int irq; + u8 rev; }; =20 static inline u32 ls_pcie_g4_lut_readl(struct ls_pcie_g4 *pcie, u32 off) @@ -76,6 +82,15 @@ static bool ls_pcie_g4_is_bridge(struct ls_pcie_g4 *pcie= ) return header_type =3D=3D PCI_HEADER_TYPE_BRIDGE; } =20 +static int ls_pcie_g4_host_init(struct mobiveil_pcie *pci) +{ + struct ls_pcie_g4 *pcie =3D to_ls_pcie_g4(pci); + + pcie->rev =3D csr_readb(pci, PCI_REVISION_ID); + + return 0; +} + static int ls_pcie_g4_link_up(struct mobiveil_pcie *pci) { struct ls_pcie_g4 *pcie =3D to_ls_pcie_g4(pci); @@ -188,12 +203,34 @@ static void ls_pcie_g4_reset(struct work_struct *work= ) ls_pcie_g4_reinit_hw(pcie); } =20 +static int ls_pcie_g4_read_other_conf(struct pci_bus *bus, unsigned int de= vfn, + int where, int size, u32 *val) +{ + struct mobiveil_pcie *pci =3D bus->sysdata; + struct ls_pcie_g4 *pcie =3D to_ls_pcie_g4(pci); + int ret; + + if (pcie->rev =3D=3D REV_1_0 && where =3D=3D PCI_VENDOR_ID) + ls_pcie_g4_lut_writel(pcie, PCIE_LUT_GCR, + 0 << PCIE_LUT_GCR_RRE); + + ret =3D pci_generic_config_read(bus, devfn, where, size, val); + + if (pcie->rev =3D=3D REV_1_0 && where =3D=3D PCI_VENDOR_ID) + ls_pcie_g4_lut_writel(pcie, PCIE_LUT_GCR, + 1 << PCIE_LUT_GCR_RRE); + + return ret; +} + static struct mobiveil_rp_ops ls_pcie_g4_rp_ops =3D { .interrupt_init =3D ls_pcie_g4_interrupt_init, + .read_other_conf =3D ls_pcie_g4_read_other_conf, }; =20 static const struct mobiveil_pab_ops ls_pcie_g4_pab_ops =3D { .link_up =3D ls_pcie_g4_link_up, + .host_init =3D ls_pcie_g4_host_init, }; =20 static int __init ls_pcie_g4_probe(struct platform_device *pdev) diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c b/drivers= /pci/controller/mobiveil/pcie-mobiveil-host.c index e8d0c4989013..5f51bc2dd6d7 100644 --- a/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c +++ b/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c @@ -79,9 +79,20 @@ static void __iomem *mobiveil_pcie_map_bus(struct pci_bu= s *bus, return pcie->rp.config_axi_slave_base + where; } =20 +static int mobiveil_pcie_config_read(struct pci_bus *bus, unsigned int dev= fn, + int where, int size, u32 *val) +{ + struct mobiveil_pcie *pcie =3D bus->sysdata; + struct root_port *rp =3D &pcie->rp; + + if (bus->number > rp->root_bus_nr && rp->ops->read_other_conf) + return rp->ops->read_other_conf(bus, devfn, where, size, val); + + return pci_generic_config_read(bus, devfn, where, size, val); +} static struct pci_ops mobiveil_pcie_ops =3D { .map_bus =3D mobiveil_pcie_map_bus, - .read =3D pci_generic_config_read, + .read =3D mobiveil_pcie_config_read, .write =3D pci_generic_config_write, }; =20 @@ -309,6 +320,10 @@ int mobiveil_host_init(struct mobiveil_pcie *pcie, boo= l reinit) value |=3D (PCI_CLASS_BRIDGE_PCI << 16); csr_writel(pcie, value, PAB_INTP_AXI_PIO_CLASS); =20 + /* Platform specific host init */ + if (pcie->ops->host_init) + return pcie->ops->host_init(pcie); + return 0; } =20 diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil.h b/drivers/pci/= controller/mobiveil/pcie-mobiveil.h index 0ccd6cee5f8f..ab43de5e4b2b 100644 --- a/drivers/pci/controller/mobiveil/pcie-mobiveil.h +++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.h @@ -145,6 +145,8 @@ struct mobiveil_msi { /* MSI information */ =20 struct mobiveil_rp_ops { int (*interrupt_init)(struct mobiveil_pcie *pcie); + int (*read_other_conf)(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 *val); }; =20 struct root_port { @@ -160,6 +162,7 @@ struct root_port { =20 struct mobiveil_pab_ops { int (*link_up)(struct mobiveil_pcie *pcie); + int (*host_init)(struct mobiveil_pcie *pcie); }; =20 struct mobiveil_pcie { --=20 2.17.1