From: Lukas Wunner <lukas@wunner.de>
To: Spencer Lingard <spencer@mellanox.com>
Cc: linux-pci@vger.kernel.org,
Mika Westerberg <mika.westerberg@linux.intel.com>,
Sergey Miroshnichenko <s.miroshnichenko@yadro.com>,
Keith Busch <keith.busch@intel.com>
Subject: Re: [PATCH] PCI: pciehp: Fix false command timeouts on boot
Date: Mon, 15 Apr 2019 04:59:08 +0200 [thread overview]
Message-ID: <20190415025908.bd45jqtp62eeuiuz@wunner.de> (raw)
In-Reply-To: <20190414193641.xo7yf4uqh7ci7lci@wunner.de>
On Sun, Apr 14, 2019 at 09:36:41PM +0200, Lukas Wunner wrote:
> I suppose this can happen if a write to the Slot Control register is
> performed while HPIE and/or CCIE is disabled, the two notifications
> are subsequently enabled and another write to the Slot Control is
> performed. That second write will then call wait_event_timeout()
> because of the stale ctrl->cmd_busy == 1, but the Command Complete
> notification has already happened and was cleared by pcie_poll_cmd(),
> hence it times out.
>
> Sounds reasonable, I'm a little suprised though that I've never seen
> this myself. I guess we've been doing this wrong for years, so:
On second thought, it's not surprising at all that I never saw this
because Thunderbolt sets NoCompl+, so doesn't use Command Complete
notifications.
I suspect that even though we've been doing this wrong for a long time,
the bug was exposed by a recent change to pciehp. Do you happen to
know since which kernel version or commit you've been witnessing the
timeouts?
Thanks,
Lukas
next prev parent reply other threads:[~2019-04-15 2:59 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-04-10 18:07 [PATCH] PCI: pciehp: Fix false command timeouts on boot Spencer Lingard
2019-04-14 19:36 ` Lukas Wunner
2019-04-15 2:59 ` Lukas Wunner [this message]
2019-04-16 18:32 ` Spencer Lingard
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