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From: Vidya Sagar <vidyas@nvidia.com>
To: <lorenzo.pieralisi@arm.com>, <robh+dt@kernel.org>,
	<bhelgaas@google.com>, <thierry.reding@gmail.com>,
	<jonathanh@nvidia.com>, <amanharitsh123@gmail.com>,
	<dinghao.liu@zju.edu.cn>, <kw@linux.com>
Cc: <linux-pci@vger.kernel.org>, <linux-tegra@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>, <kthota@nvidia.com>,
	<mmaddireddy@nvidia.com>, <vidyas@nvidia.com>,
	<sagar.tv@gmail.com>
Subject: [PATCH V4 6/6] PCI: tegra: Disable LTSSM during L2 entry
Date: Mon, 9 Nov 2020 22:49:37 +0530	[thread overview]
Message-ID: <20201109171937.28326-7-vidyas@nvidia.com> (raw)
In-Reply-To: <20201109171937.28326-1-vidyas@nvidia.com>

PCIe cards like Marvell SATA controller and some of the Samsung NVMe
drives don't support taking the link to L2 state. When the link doesn't
go to L2 state, Tegra194 requires the LTSSM to be disabled to allow PHY
to start the next link up process cleanly during suspend/resume sequence.
Failing to disable LTSSM results in the PCIe link not coming up in the
next resume cycle.

Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
---
V4:
* New patch in this series

 drivers/pci/controller/dwc/pcie-tegra194.c | 16 +++++++++-------
 1 file changed, 9 insertions(+), 7 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index 8c08998b9ce1..57ff0657bbe2 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -1513,6 +1513,14 @@ static void tegra_pcie_dw_pme_turnoff(struct tegra_pcie_dw *pcie)
 		data &= ~APPL_PINMUX_PEX_RST;
 		appl_writel(pcie, data, APPL_PINMUX);
 
+		/*
+		 * Some cards do not go to detect state even after de-asserting
+		 * PERST#. So, de-assert LTSSM to bring link to detect state.
+		 */
+		data = readl(pcie->appl_base + APPL_CTRL);
+		data &= ~APPL_CTRL_LTSSM_EN;
+		writel(data, pcie->appl_base + APPL_CTRL);
+
 		err = readl_poll_timeout_atomic(pcie->appl_base + APPL_DEBUG,
 						data,
 						((data &
@@ -1520,14 +1528,8 @@ static void tegra_pcie_dw_pme_turnoff(struct tegra_pcie_dw *pcie)
 						APPL_DEBUG_LTSSM_STATE_SHIFT) ==
 						LTSSM_STATE_PRE_DETECT,
 						1, LTSSM_TIMEOUT);
-		if (err) {
+		if (err)
 			dev_info(pcie->dev, "Link didn't go to detect state\n");
-		} else {
-			/* Disable LTSSM after link is in detect state */
-			data = appl_readl(pcie, APPL_CTRL);
-			data &= ~APPL_CTRL_LTSSM_EN;
-			appl_writel(pcie, data, APPL_CTRL);
-		}
 	}
 	/*
 	 * DBI registers may not be accessible after this as PLL-E would be
-- 
2.17.1


  parent reply	other threads:[~2020-11-09 17:20 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-11-09 17:19 [PATCH V4 0/6] Enhancements to Tegra194 PCIe driver Vidya Sagar
2020-11-09 17:19 ` [PATCH V4 1/6] PCI: tegra: Fix ASPM-L1SS advertisement disable code Vidya Sagar
2020-11-26 11:33   ` Thierry Reding
2020-12-03 12:36     ` Vidya Sagar
2020-11-09 17:19 ` [PATCH V4 2/6] PCI: tegra: Map configuration space as nGnRnE Vidya Sagar
2020-11-26 11:33   ` Thierry Reding
2020-12-03 12:56     ` Vidya Sagar
2020-11-09 17:19 ` [PATCH V4 3/6] PCI: tegra: Set DesignWare IP version Vidya Sagar
2020-11-26 11:34   ` Thierry Reding
2020-11-09 17:19 ` [PATCH V4 4/6] PCI: tegra: Continue unconfig sequence even if parts fail Vidya Sagar
2020-11-26 11:34   ` Thierry Reding
2020-11-30 12:10   ` Lorenzo Pieralisi
2020-12-01 14:24     ` Thierry Reding
2020-12-01 14:44       ` Lorenzo Pieralisi
2020-11-09 17:19 ` [PATCH V4 5/6] PCI: tegra: Check return value of tegra_pcie_init_controller() Vidya Sagar
2020-11-26 11:34   ` Thierry Reding
2020-11-09 17:19 ` Vidya Sagar [this message]
2020-11-26 11:34   ` [PATCH V4 6/6] PCI: tegra: Disable LTSSM during L2 entry Thierry Reding
2020-11-25 17:57 ` [PATCH V4 0/6] Enhancements to Tegra194 PCIe driver Thierry Reding
2020-11-25 19:51   ` Vidya Sagar
2020-11-26 11:31     ` Thierry Reding

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