From: Kishon Vijay Abraham I <kishon@ti.com>
To: Bjorn Helgaas <bhelgaas@google.com>,
Rob Herring <robh+dt@kernel.org>, Tero Kristo <t-kristo@ti.com>,
Nishanth Menon <nm@ti.com>,
Kishon Vijay Abraham I <kishon@ti.com>,
Tom Joseph <tjoseph@cadence.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: <linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-omap@vger.kernel.org>
Subject: [PATCH v2 1/3] dt-bindings: pci: ti,j721e: Fix "ti,syscon-pcie-ctrl" to take argument
Date: Fri, 4 Dec 2020 13:21:15 +0530 [thread overview]
Message-ID: <20201204075117.10430-2-kishon@ti.com> (raw)
In-Reply-To: <20201204075117.10430-1-kishon@ti.com>
Fix binding documentation of "ti,syscon-pcie-ctrl" to take phandle with
argument. The argument is the register offset within "syscon" used to
configure PCIe controller. This change is as discussed in [1]
[1] -> http://lore.kernel.org/r/CAL_JsqKiUcO76bo1GoepWM1TusJWoty_BRy2hFSgtEVMqtrvvQ@mail.gmail.com
Fixes: 431b53b81cdc ("dt-bindings: PCI: Add host mode dt-bindings for TI's J721E SoC")
Fixes: 45b39e928966 ("dt-bindings: PCI: Add EP mode dt-bindings for TI's J721E SoC")
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
.../devicetree/bindings/pci/ti,j721e-pci-ep.yaml | 11 +++++++----
.../devicetree/bindings/pci/ti,j721e-pci-host.yaml | 11 +++++++----
2 files changed, 14 insertions(+), 8 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml
index 3ae3e1a2d4b0..3766565cf258 100644
--- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml
+++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml
@@ -29,9 +29,12 @@ properties:
- const: mem
ti,syscon-pcie-ctrl:
- description: Phandle to the SYSCON entry required for configuring PCIe mode
- and link speed.
- $ref: /schemas/types.yaml#/definitions/phandle
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ - items:
+ - description: Phandle to the SYSCON entry
+ - description: pcie_ctrl register offset within SYSCON
+ description: Specifier for configuring PCIe mode and link speed.
power-domains:
maxItems: 1
@@ -80,7 +83,7 @@ examples:
<0x00 0x0d000000 0x00 0x00800000>,
<0x00 0x10000000 0x00 0x08000000>;
reg-names = "intd_cfg", "user_cfg", "reg", "mem";
- ti,syscon-pcie-ctrl = <&pcie0_ctrl>;
+ ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x4070>;
max-link-speed = <3>;
num-lanes = <2>;
power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml
index ee7a8eade3f6..2b6a1a5eaf7a 100644
--- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml
+++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml
@@ -29,9 +29,12 @@ properties:
- const: cfg
ti,syscon-pcie-ctrl:
- description: Phandle to the SYSCON entry required for configuring PCIe mode
- and link speed.
- $ref: /schemas/types.yaml#/definitions/phandle
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ - items:
+ - description: Phandle to the SYSCON entry
+ - description: pcie_ctrl register offset within SYSCON
+ description: Specifier for configuring PCIe mode and link speed.
power-domains:
maxItems: 1
@@ -90,7 +93,7 @@ examples:
<0x00 0x0d000000 0x00 0x00800000>,
<0x00 0x10000000 0x00 0x00001000>;
reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
- ti,syscon-pcie-ctrl = <&pcie0_ctrl>;
+ ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x4070>;
max-link-speed = <3>;
num-lanes = <2>;
power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
--
2.17.1
next prev parent reply other threads:[~2020-12-04 7:53 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-04 7:51 [PATCH v2 0/3] PCI: J721E: Fix Broken DT w.r.t SYSCON DT Kishon Vijay Abraham I
2020-12-04 7:51 ` Kishon Vijay Abraham I [this message]
2020-12-07 14:29 ` [PATCH v2 1/3] dt-bindings: pci: ti,j721e: Fix "ti,syscon-pcie-ctrl" to take argument Rob Herring
2020-12-04 7:51 ` [PATCH v2 2/3] PCI: j721e: Get offset within "syscon" from "ti,syscon-pcie-ctrl" phandle arg Kishon Vijay Abraham I
2020-12-07 14:30 ` Rob Herring
2020-12-04 7:51 ` [PATCH v2 3/3] arm64: dts: ti: k3-j721e-main: Remove "syscon" nodes added for pcieX_ctrl Kishon Vijay Abraham I
2020-12-07 14:31 ` Rob Herring
2020-12-10 6:47 ` [PATCH v2 0/3] PCI: J721E: Fix Broken DT w.r.t SYSCON DT Kishon Vijay Abraham I
2020-12-10 12:39 ` Kishon Vijay Abraham I
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