From: <daire.mcnamara@microchip.com>
To: <lorenzo.pieralisi@arm.com>, <bhelgaas@google.com>,
<robh@kernel.org>, <linux-pci@vger.kernel.org>,
<robh+dt@kernel.org>, <devicetree@vger.kernel.org>
Cc: <david.abdurachmanov@gmail.com>, <cyril.jean@microchip.com>,
"Daire McNamara" <daire.mcnamara@microchip.com>
Subject: [PATCH v21 2/4] dt-bindings: PCI: microchip: Add Microchip PolarFire host binding
Date: Mon, 25 Jan 2021 16:29:32 +0000 [thread overview]
Message-ID: <20210125162934.5335-3-daire.mcnamara@microchip.com> (raw)
In-Reply-To: <20210125162934.5335-1-daire.mcnamara@microchip.com>
From: Daire McNamara <daire.mcnamara@microchip.com>
Add device tree bindings for the Microchip PolarFire PCIe controller
when configured in host (Root Complex) mode.
Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
.../bindings/pci/microchip,pcie-host.yaml | 92 +++++++++++++++++++
1 file changed, 92 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml
diff --git a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml
new file mode 100644
index 000000000000..04251d71f56b
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml
@@ -0,0 +1,92 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/microchip,pcie-host.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip PCIe Root Port Bridge Controller Device Tree Bindings
+
+maintainers:
+ - Daire McNamara <daire.mcnamara@microchip.com>
+
+allOf:
+ - $ref: /schemas/pci/pci-bus.yaml#
+
+properties:
+ compatible:
+ const: microchip,pcie-host-1.0 # PolarFire
+
+ reg:
+ maxItems: 2
+
+ reg-names:
+ items:
+ - const: cfg
+ - const: apb
+
+ interrupts:
+ minItems: 1
+ maxItems: 2
+ items:
+ - description: PCIe host controller
+ - description: builtin MSI controller
+
+ interrupt-names:
+ minItems: 1
+ maxItems: 2
+ items:
+ - const: pcie
+ - const: msi
+
+ ranges:
+ maxItems: 1
+
+ msi-controller:
+ description: Identifies the node as an MSI controller.
+
+ msi-parent:
+ description: MSI controller the device is capable of using.
+
+required:
+ - reg
+ - reg-names
+ - "#interrupt-cells"
+ - interrupts
+ - interrupt-map-mask
+ - interrupt-map
+ - msi-controller
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ pcie0: pcie@2030000000 {
+ compatible = "microchip,pcie-host-1.0";
+ reg = <0x0 0x70000000 0x0 0x08000000>,
+ <0x0 0x43000000 0x0 0x00010000>;
+ reg-names = "cfg", "apb";
+ device_type = "pci";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ interrupts = <119>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+ interrupt-map = <0 0 0 1 &pcie_intc0 0>,
+ <0 0 0 2 &pcie_intc0 1>,
+ <0 0 0 3 &pcie_intc0 2>,
+ <0 0 0 4 &pcie_intc0 3>;
+ interrupt-parent = <&plic0>;
+ msi-parent = <&pcie0>;
+ msi-controller;
+ bus-range = <0x00 0x7f>;
+ ranges = <0x03000000 0x0 0x78000000 0x0 0x78000000 0x0 0x04000000>;
+ pcie_intc0: interrupt-controller {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+ };
--
2.25.1
next prev parent reply other threads:[~2021-01-25 16:32 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-25 16:29 [PATCH v21 0/4] PCI: microchip: Add host driver for Microchip PCIe controller daire.mcnamara
2021-01-25 16:29 ` [PATCH v21 1/4] PCI: Call platform_set_drvdata earlier in devm_pci_alloc_host_bridge daire.mcnamara
2021-01-25 16:29 ` daire.mcnamara [this message]
2021-01-25 16:29 ` [PATCH v21 3/4] PCI: microchip: Add host driver for Microchip PCIe controller daire.mcnamara
2021-02-01 19:05 ` Lorenzo Pieralisi
[not found] ` <MN2PR11MB42691AE1B54DEAB5C1BAA11D96B59@MN2PR11MB4269.namprd11.prod.outlook.com>
2021-02-04 10:20 ` Lorenzo Pieralisi
2021-02-10 13:07 ` Geert Uytterhoeven
2021-02-11 13:03 ` Ben Dooks
2021-02-11 13:07 ` Geert Uytterhoeven
2021-02-16 9:54 ` Daire.McNamara
2022-01-27 20:20 ` Bjorn Helgaas
2022-01-28 9:55 ` Marc Zyngier
2022-01-28 13:16 ` Bjorn Helgaas
2021-01-25 16:29 ` [PATCH v21 4/4] MAINTAINERS: Add Daire McNamara as maintainer for the Microchip PCIe driver daire.mcnamara
2021-02-04 11:42 ` [PATCH v21 0/4] PCI: microchip: Add host driver for Microchip PCIe controller Lorenzo Pieralisi
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20210125162934.5335-3-daire.mcnamara@microchip.com \
--to=daire.mcnamara@microchip.com \
--cc=bhelgaas@google.com \
--cc=cyril.jean@microchip.com \
--cc=david.abdurachmanov@gmail.com \
--cc=devicetree@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=lorenzo.pieralisi@arm.com \
--cc=robh+dt@kernel.org \
--cc=robh@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).