From: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
To: <linux-pci@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Cc: <bhelgaas@google.com>,
Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
Subject: [PATCH v3 2/2] PCI: xilinx-nwl: Add optional "dma-coherent" property
Date: Mon, 22 Feb 2021 14:17:32 +0530 [thread overview]
Message-ID: <20210222084732.21521-2-bharat.kumar.gogada@xilinx.com> (raw)
In-Reply-To: <20210222084732.21521-1-bharat.kumar.gogada@xilinx.com>
Add optional dma-coherent property to support coherent PCIe DMA traffic.
Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
---
Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt b/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt
index 01bf7fdf4c19..2d677e90a7e2 100644
--- a/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt
@@ -33,6 +33,8 @@ Required properties:
- #address-cells: specifies the number of cells needed to encode an
address. The value must be 0.
+Optional properties:
+- dma-coherent: present if DMA operations are coherent
Example:
++++++++
--
2.17.1
next prev parent reply other threads:[~2021-02-22 8:49 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-22 8:47 [PATCH v3 1/2] PCI: xilinx-nwl: Enable coherent PCIe DMA traffic using CCI Bharat Kumar Gogada
2021-02-22 8:47 ` Bharat Kumar Gogada [this message]
2021-03-15 6:12 ` Bharat Kumar Gogada
2021-03-23 11:17 ` Bharat Kumar Gogada
2021-04-02 5:31 ` Bharat Kumar Gogada
2021-04-06 14:20 ` Lorenzo Pieralisi
2021-04-06 20:34 ` Rob Herring
2021-04-07 16:01 ` Lorenzo Pieralisi
2021-04-08 15:58 ` Bharat Kumar Gogada
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