From: Kishon Vijay Abraham I <kishon@ti.com>
To: Kishon Vijay Abraham I <kishon@ti.com>,
Bjorn Helgaas <bhelgaas@google.com>,
Rob Herring <robh+dt@kernel.org>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Marc Zyngier <maz@kernel.org>
Cc: <linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
Lokesh Vutla <lokeshvutla@ti.com>
Subject: [PATCH 1/6] dt-bindings: PCI: ti,am65: Add PCIe host mode dt-bindings for TI's AM65 SoC
Date: Thu, 25 Mar 2021 14:30:21 +0530 [thread overview]
Message-ID: <20210325090026.8843-2-kishon@ti.com> (raw)
In-Reply-To: <20210325090026.8843-1-kishon@ti.com>
Add PCIe host mode dt-bindings for TI's AM65 SoC.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
.../bindings/pci/ti,am65-pci-host.yaml | 111 ++++++++++++++++++
1 file changed, 111 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml
diff --git a/Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml b/Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml
new file mode 100644
index 000000000000..b77e492886fa
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml
@@ -0,0 +1,111 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/pci/ti,am65-pci-host.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: TI AM65 PCI Host
+
+maintainers:
+ - Kishon Vijay Abraham I <kishon@ti.com>
+
+allOf:
+ - $ref: /schemas/pci/pci-bus.yaml#
+
+properties:
+ compatible:
+ enum:
+ - ti,am654-pcie-rc
+
+ reg:
+ maxItems: 4
+
+ reg-names:
+ items:
+ - const: app
+ - const: dbics
+ - const: config
+ - const: atu
+
+ power-domains:
+ maxItems: 1
+
+ ti,syscon-pcie-id:
+ description: Phandle to the SYSCON entry required for getting PCIe device/vendor ID
+ $ref: /schemas/types.yaml#/definitions/phandle
+
+ ti,syscon-pcie-mode:
+ description: Phandle to the SYSCON entry required for configuring PCIe in RC or EP mode.
+ $ref: /schemas/types.yaml#/definitions/phandle
+
+ msi-map: true
+
+ dma-coherent: true
+
+patternProperties:
+ "interrupt-controller":
+ type: object
+ description: interrupt controller to handle legacy interrupts.
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - max-link-speed
+ - num-lanes
+ - power-domains
+ - ti,syscon-pcie-id
+ - ti,syscon-pcie-mode
+ - msi-map
+ - ranges
+ - reset-gpios
+ - phys
+ - phy-names
+ - dma-coherent
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/soc/ti,sci_pm_domain.h>
+ #include <dt-bindings/gpio/gpio.h>
+
+ bus {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pcie0_rc: pcie@5500000 {
+ compatible = "ti,am654-pcie-rc";
+ reg = <0x0 0x5500000 0x0 0x1000>,
+ <0x0 0x5501000 0x0 0x1000>,
+ <0x0 0x10000000 0x0 0x2000>,
+ <0x0 0x5506000 0x0 0x1000>;
+ reg-names = "app", "dbics", "config", "atu";
+ power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x81000000 0 0 0x0 0x10020000 0 0x00010000>,
+ <0x82000000 0 0x10030000 0x0 0x10030000 0 0x07FD0000>;
+ ti,syscon-pcie-id = <&pcie_devid>;
+ ti,syscon-pcie-mode = <&pcie0_mode>;
+ bus-range = <0x0 0xff>;
+ num-viewport = <16>;
+ max-link-speed = <2>;
+ dma-coherent;
+ interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
+ msi-map = <0x0 &gic_its 0x0 0x10000>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie0_intc 0>, /* INT A */
+ <0 0 0 2 &pcie0_intc 0>, /* INT B */
+ <0 0 0 3 &pcie0_intc 0>, /* INT C */
+ <0 0 0 4 &pcie0_intc 0>; /* INT D */
+
+ pcie0_intc: interrupt-controller {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>;
+ };
+ };
--
2.17.1
next prev parent reply other threads:[~2021-03-25 9:01 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-25 9:00 [PATCH 0/6] PCI: Add legacy interrupt support in Keystone Kishon Vijay Abraham I
2021-03-25 9:00 ` Kishon Vijay Abraham I [this message]
2021-03-25 16:56 ` [PATCH 1/6] dt-bindings: PCI: ti, am65: Add PCIe host mode dt-bindings for TI's AM65 SoC Rob Herring
2021-03-25 23:38 ` [PATCH 1/6] dt-bindings: PCI: ti,am65: " Rob Herring
2021-03-30 9:29 ` Kishon Vijay Abraham I
2021-04-20 13:13 ` Rob Herring
2021-03-25 9:00 ` [PATCH 2/6] dt-bindings: PCI: ti,am65: Add PCIe endpoint " Kishon Vijay Abraham I
2021-03-25 16:56 ` [PATCH 2/6] dt-bindings: PCI: ti, am65: " Rob Herring
2021-03-25 9:00 ` [PATCH 3/6] irqdomain: Export of_phandle_args_to_fwspec() Kishon Vijay Abraham I
2021-03-25 9:00 ` [PATCH 4/6] PCI: keystone: Convert to using hierarchy domain for legacy interrupts Kishon Vijay Abraham I
2021-03-26 6:58 ` Krzysztof Wilczyński
2021-03-25 9:00 ` [PATCH 5/6] PCI: keystone: Add PCI legacy interrupt support for AM654 Kishon Vijay Abraham I
2021-03-26 7:14 ` Krzysztof Wilczyński
2021-04-02 11:11 ` Marc Zyngier
2021-03-25 9:00 ` [PATCH 6/6] PCI: keystone: Add workaround for Errata #i2037 (AM65x SR 1.0) Kishon Vijay Abraham I
2021-03-26 7:19 ` Krzysztof Wilczyński
2021-05-17 13:15 ` [PATCH 0/6] PCI: Add legacy interrupt support in Keystone Christian Gmeiner
2021-05-17 13:21 ` Kishon Vijay Abraham I
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