From: kernel test robot <lkp@intel.com>
To: Dan Williams <dan.j.williams@intel.com>, linux-cxl@vger.kernel.org
Cc: kbuild-all@lists.01.org, linux-pci@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org
Subject: Re: [PATCH 7/8] cxl/port: Introduce cxl_port objects
Date: Sat, 8 May 2021 10:24:07 +0800 [thread overview]
Message-ID: <202105081033.ykE7bfNp-lkp@intel.com> (raw)
In-Reply-To: <162042791852.1202325.8197739881935753009.stgit@dwillia2-desk3.amr.corp.intel.com>
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Hi Dan,
I love your patch! Perhaps something to improve:
[auto build test WARNING on a38fd8748464831584a19438cbb3082b5a2dab15]
url: https://github.com/0day-ci/linux/commits/Dan-Williams/CXL-Port-Enumeration-and-Plans-for-v5-14/20210508-065317
base: a38fd8748464831584a19438cbb3082b5a2dab15
config: i386-randconfig-a003-20210507 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
reproduce (this is a W=1 build):
# https://github.com/0day-ci/linux/commit/10f83390eae24effd86455f46429d03ae7c35f53
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Dan-Williams/CXL-Port-Enumeration-and-Plans-for-v5-14/20210508-065317
git checkout 10f83390eae24effd86455f46429d03ae7c35f53
# save the attached .config to linux build tree
make W=1 W=1 ARCH=i386
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All warnings (new ones prefixed by >>):
drivers/cxl/acpi.c: In function 'cxl_acpi_register_ports':
>> drivers/cxl/acpi.c:76:55: warning: conversion from 'long long unsigned int' to 'resource_size_t' {aka 'unsigned int'} changes value from '18446744073709551615' to '4294967295' [-Woverflow]
76 | port = devm_cxl_add_port(dev, port, &root->dev, idx, ~0ULL);
| ^~~~~
vim +76 drivers/cxl/acpi.c
61
62 /*
63 * A host bridge may contain one or more root ports. Register each port
64 * as a child of the cxl_root.
65 */
66 static int cxl_acpi_register_ports(struct device *dev, struct acpi_device *root,
67 struct cxl_port *port, int idx)
68 {
69 struct acpi_pci_root *pci_root = acpi_pci_find_root(root->handle);
70 struct cxl_walk_context ctx;
71
72 if (!pci_root)
73 return -ENXIO;
74
75 /* TODO: fold in CEDT.CHBS retrieval */
> 76 port = devm_cxl_add_port(dev, port, &root->dev, idx, ~0ULL);
77 if (IS_ERR(port))
78 return PTR_ERR(port);
79 dev_dbg(dev, "%s: register: %s\n", dev_name(&root->dev),
80 dev_name(&port->dev));
81
82 ctx = (struct cxl_walk_context) {
83 .dev = dev,
84 .root = pci_root->bus,
85 .port = port,
86 };
87 pci_walk_bus(pci_root->bus, match_add_root_ports, &ctx);
88
89 if (ctx.count == 0)
90 return -ENODEV;
91 return ctx.error;
92 }
93
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
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next prev parent reply other threads:[~2021-05-08 2:25 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-07 22:51 [PATCH v3 0/8] CXL Port Enumeration and Plans for v5.14 Dan Williams
2021-05-07 22:51 ` [PATCH 1/8] cxl/mem: Move some definitions to mem.h Dan Williams
2021-05-10 15:14 ` Jonathan Cameron
2021-05-12 6:20 ` Dan Williams
2021-05-07 22:51 ` [PATCH 2/8] cxl/mem: Introduce 'struct cxl_regs' for "composable" CXL devices Dan Williams
2021-05-10 15:17 ` Jonathan Cameron
2021-05-12 6:26 ` Dan Williams
2021-05-07 22:51 ` [PATCH 3/8] cxl/core: Rename bus.c to core.c Dan Williams
2021-05-10 15:17 ` Jonathan Cameron
2021-05-07 22:51 ` [PATCH 4/8] cxl/core: Refactor CXL register lookup for bridge reuse Dan Williams
2021-05-07 22:51 ` [PATCH 5/8] cxl/acpi: Introduce ACPI0017 driver and cxl_root Dan Williams
2021-05-10 14:56 ` Jonathan Cameron
2021-05-12 6:29 ` Dan Williams
2021-05-07 22:51 ` [PATCH 6/8] cxl/Kconfig: Default drivers to CONFIG_CXL_BUS Dan Williams
2021-05-10 15:18 ` Jonathan Cameron
2021-05-07 22:51 ` [PATCH 7/8] cxl/port: Introduce cxl_port objects Dan Williams
2021-05-08 2:24 ` kernel test robot [this message]
2021-05-10 15:21 ` Jonathan Cameron
2021-05-12 6:36 ` Dan Williams
2021-05-07 22:52 ` [PATCH 8/8] cxl/acpi: Add module parameters to stand in for ACPI tables Dan Williams
2021-05-10 17:22 ` [PATCH v3 0/8] CXL Port Enumeration and Plans for v5.14 Jonathan Cameron
2021-05-10 17:31 ` Dan Williams
-- strict thread matches above, loose matches on Subject: below --
2021-03-24 21:30 [PATCH 0/8] CXL Port Enumeration Dan Williams
2021-03-24 21:31 ` [PATCH 7/8] cxl/port: Introduce cxl_port objects Dan Williams
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