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From: Ben Widawsky <ben.widawsky@intel.com>
To: linux-pci@vger.kernel.org
Cc: "Martin Mareš" <mj@ucw.cz>,
	"Dan Williams" <dan.j.williams@intel.com>,
	"Ben Widawsky" <ben.widawsky@intel.com>
Subject: [PATCH 7/9] cxl: Add support for DVSEC port cap
Date: Fri,  4 Jun 2021 12:05:39 -0700	[thread overview]
Message-ID: <20210604190541.175602-8-ben.widawsky@intel.com> (raw)
In-Reply-To: <20210604190541.175602-1-ben.widawsky@intel.com>

Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
---
 lib/header.h | 11 +++++++++++
 ls-ecaps.c   | 43 +++++++++++++++++++++++++++++++++++++------
 2 files changed, 48 insertions(+), 6 deletions(-)

diff --git a/lib/header.h b/lib/header.h
index c346548..8141e13 100644
--- a/lib/header.h
+++ b/lib/header.h
@@ -1109,6 +1109,17 @@
 #define PCI_CXL_DEV_RANGE2_BASE_HI	0x30
 #define PCI_CXL_DEV_RANGE2_BASE_LO	0x34
 
+/* PCIe CXL 2.0 Designated Vendor-Specific Capabilities for Ports */
+#define PCI_CXL_PORT_EXT_STATUS 0x0a		/* Port Extension Status */
+#define  PCI_CXL_PORT_PM_INIT_COMPLETE 0x1	/* Port Power Management Initialization Complete */
+#define PCI_CXL_PORT_CTRL 0x0c			/* Port Control Override */
+#define  PCI_CXL_PORT_UNMASK_SBR 0x0001		/* Unmask SBR */
+#define  PCI_CXL_PORT_UNMASK_LINK 0x0002	/* Unmask Link Disable */
+#define  PCI_CXL_PORT_ALT_MEMORY 0x0004		/* Alt Memory and ID Space Enable */
+#define  PCI_CXL_PORT_ALT_BME 0x0008		/* Alt BME */
+#define PCI_CXL_PORT_ALT_BUS_BASE 0xe
+#define PCI_CXL_PORT_ALT_BUS_LIMIT 0xf
+
 /* Access Control Services */
 #define PCI_ACS_CAP		0x04	/* ACS Capability Register */
 #define PCI_ACS_CAP_VALID	0x0001	/* ACS Source Validation */
diff --git a/ls-ecaps.c b/ls-ecaps.c
index 8072bbe..b11d5a9 100644
--- a/ls-ecaps.c
+++ b/ls-ecaps.c
@@ -778,6 +778,28 @@ dvsec_cxl_device(uint8_t *data, int rev)
   cxl_range(range_base, range_size, 2);
 }
 
+static void
+dvsec_cxl_port(uint8_t* data, int rev)
+{
+  u16 w;
+  u8 b1, b2;
+
+  if (rev != 0)
+    return;
+
+  w = *(u16 *)(data + PCI_CXL_PORT_EXT_STATUS);
+  printf("\t\tCXLPortSta:\tPMComplete%c\n", FLAG(w, PCI_CXL_PORT_EXT_STATUS));
+
+  w = *(u16 *)(data + PCI_CXL_PORT_CTRL);
+  printf("\t\tCXLPortCtl:\tUnmaskSBR%c UnmaskLinkDisable%c AltMem%c AltBME%c\n",
+    FLAG(w, PCI_CXL_PORT_UNMASK_SBR), FLAG(w, PCI_CXL_PORT_UNMASK_LINK),
+    FLAG(w, PCI_CXL_PORT_ALT_MEMORY), FLAG(w, PCI_CXL_PORT_ALT_BME));
+
+  b1 = *(u8 *)(data + PCI_CXL_PORT_ALT_BUS_BASE);
+  b2 = *(u8 *)(data + PCI_CXL_PORT_ALT_BUS_LIMIT);
+  printf("\t\tAlternateBus: %02x-%02x\n", b1, b2);
+}
+
 static void
 cap_dvsec_cxl(struct device *d, int id, int where)
 {
@@ -787,15 +809,24 @@ cap_dvsec_cxl(struct device *d, int id, int where)
   if (verbose < 2)
     return;
 
-  if (id != 0)
-    return;
-
   rev = BITS(get_conf_byte(d, where + 0x6), 0, 4);
 
-  if (!config_fetch(d, where, 0x38))
-    return;
+  switch (id) {
+    case 0:
+      if (!config_fetch(d, where, 0x38))
+        return;
+
+      dvsec_cxl_device(d->config + where, rev);
+      break;
+    case 3:
+      if (!config_fetch(d, where, 0x28))
+        return;
 
-  dvsec_cxl_device(d->config + where, rev);
+      dvsec_cxl_port(d->config + where, rev);
+      break;
+    default:
+      break;
+  }
 }
 
 static void
-- 
2.31.1


  parent reply	other threads:[~2021-06-04 19:05 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-04 19:05 [PATCH 0/9] Add CXL 2.0 DVSEC Decoding Ben Widawsky
2021-06-04 19:05 ` [PATCH 1/9] cxl: Rename variable to match other code Ben Widawsky
2021-06-04 19:05 ` [PATCH 2/9] cxl: Make id check more explicit Ben Widawsky
2021-06-04 19:05 ` [PATCH 3/9] cxl: Collect all DVSEC Device fields Ben Widawsky
2021-06-04 19:05 ` [PATCH 4/9] cxl: Rework caps to new function Ben Widawsky
2021-06-04 19:05 ` [PATCH 5/9] cxl: Rename caps to be device caps Ben Widawsky
2021-06-04 19:05 ` [PATCH 6/9] cxl: Implement more device DVSEC decoding Ben Widawsky
2021-06-07 16:10   ` [PATCH v2 " Ben Widawsky
2021-06-04 19:05 ` Ben Widawsky [this message]
2021-06-04 19:05 ` [PATCH 8/9] cxl: Add DVSEC Register Locator Ben Widawsky
2021-06-04 19:05 ` [PATCH 9/9] cxl: Add placeholder for undecoded DVSECs Ben Widawsky

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