From: Amey Narkhede <ameynarkhede03@gmail.com>
To: Bjorn Helgaas <helgaas@kernel.org>
Cc: alex.williamson@redhat.com,
Raphael Norwitz <raphael.norwitz@nutanix.com>,
linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
kw@linux.com, Shanker Donthineni <sdonthineni@nvidia.com>,
Sinan Kaya <okaya@kernel.org>, Len Brown <lenb@kernel.org>,
"Rafael J .Wysocki" <rjw@rjwysocki.net>,
Christoph Hellwig <hch@lst.de>
Subject: Re: [PATCH v7 1/8] PCI: Add pcie_reset_flr to follow calling convention of other reset methods
Date: Fri, 18 Jun 2021 22:02:23 +0530 [thread overview]
Message-ID: <20210618163223.otdhrkxnyng32okp@archlinux> (raw)
In-Reply-To: <20210617215734.GA3135430@bjorn-Precision-5520>
On 21/06/17 04:57PM, Bjorn Helgaas wrote:
> [+cc Christoph, since he added pcie_flr()]
>
> On Tue, Jun 08, 2021 at 11:18:50AM +0530, Amey Narkhede wrote:
> > Currently there is separate function pcie_has_flr() to probe if pcie flr is
> > supported by the device which does not match the calling convention
> > followed by reset methods which use second function argument to decide
> > whether to probe or not. Add new function pcie_reset_flr() that follows
> > the calling convention of reset methods.
>
> I don't like the fact that we handle FLR differently from other types
> of reset, so I do like the fact that this makes them more consistent.
>
> > Reviewed-by: Alex Williamson <alex.williamson@redhat.com>
> > Reviewed-by: Raphael Norwitz <raphael.norwitz@nutanix.com>
> > Co-developed-by: Alex Williamson <alex.williamson@redhat.com>
> > Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
> > Signed-off-by: Amey Narkhede <ameynarkhede03@gmail.com>
> > ---
> > drivers/crypto/cavium/nitrox/nitrox_main.c | 4 +-
> > drivers/pci/pci.c | 62 ++++++++++++----------
> > drivers/pci/pcie/aer.c | 12 ++---
> > drivers/pci/quirks.c | 9 ++--
> > include/linux/pci.h | 2 +-
> > 5 files changed, 43 insertions(+), 46 deletions(-)
> >
> > diff --git a/drivers/crypto/cavium/nitrox/nitrox_main.c b/drivers/crypto/cavium/nitrox/nitrox_main.c
> > index facc8e6bc..15d6c8452 100644
> > --- a/drivers/crypto/cavium/nitrox/nitrox_main.c
> > +++ b/drivers/crypto/cavium/nitrox/nitrox_main.c
> > @@ -306,9 +306,7 @@ static int nitrox_device_flr(struct pci_dev *pdev)
> > return -ENOMEM;
> > }
> >
> > - /* check flr support */
> > - if (pcie_has_flr(pdev))
> > - pcie_flr(pdev);
> > + pcie_reset_flr(pdev, 0);
> >
> > pci_restore_state(pdev);
> >
> > diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
> > index 452351025..3bf36924c 100644
> > --- a/drivers/pci/pci.c
> > +++ b/drivers/pci/pci.c
> > @@ -4611,32 +4611,12 @@ int pci_wait_for_pending_transaction(struct pci_dev *dev)
> > }
> > EXPORT_SYMBOL(pci_wait_for_pending_transaction);
> >
> > -/**
> > - * pcie_has_flr - check if a device supports function level resets
> > - * @dev: device to check
> > - *
> > - * Returns true if the device advertises support for PCIe function level
> > - * resets.
> > - */
> > -bool pcie_has_flr(struct pci_dev *dev)
> > -{
> > - u32 cap;
> > -
> > - if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET)
> > - return false;
> > -
> > - pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap);
> > - return cap & PCI_EXP_DEVCAP_FLR;
> > -}
> > -EXPORT_SYMBOL_GPL(pcie_has_flr);
> > -
> > /**
> > * pcie_flr - initiate a PCIe function level reset
> > * @dev: device to reset
> > *
> > - * Initiate a function level reset on @dev. The caller should ensure the
> > - * device supports FLR before calling this function, e.g. by using the
> > - * pcie_has_flr() helper.
> > + * Initiate a function level reset unconditionally on @dev without
> > + * checking any flags and DEVCAP
> > */
> > int pcie_flr(struct pci_dev *dev)
> > {
> > @@ -4659,6 +4639,31 @@ int pcie_flr(struct pci_dev *dev)
> > }
> > EXPORT_SYMBOL_GPL(pcie_flr);
> >
> > +/**
> > + * pcie_reset_flr - initiate a PCIe function level reset
> > + * @dev: device to reset
> > + * @probe: If set, only check if the device can be reset this way.
> > + *
> > + * Initiate a function level reset on @dev.
> > + */
> > +int pcie_reset_flr(struct pci_dev *dev, int probe)
> > +{
> > + u32 cap;
> > +
> > + if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET)
> > + return -ENOTTY;
> > +
> > + pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap);
> > + if (!(cap & PCI_EXP_DEVCAP_FLR))
> > + return -ENOTTY;
> > +
> > + if (probe)
> > + return 0;
> > +
> > + return pcie_flr(dev);
>
> Christoph added pcie_flr() with a60a2b73ba69 ("PCI: Export
> pcie_flr()"), where the commit log says he split out the probing
> because "non-core callers already know their hardware."
>
> It *is* reasonable to expect that drivers know whether their device
> supports FLR so they don't need to probe.
>
> But we don't expose the "probe" argument outside the PCI core for any
> other reset methods, and I would like to avoid that here.
>
> It seems excessive to have to read PCI_EXP_DEVCAP every time.
> PCI_EXP_DEVCAP_FLR is a read-only bit, and we should only need to look
> at it once.
>
> What I would really like here is a single bit in the pci_dev that we
> could set at enumeration-time, e.g., something like this:
>
> struct pci_dev {
> ...
> unsigned int has_flr:1;
> };
>
> void set_pcie_port_type(...) # during enumeration
> {
> pci_read_config_word(dev, pos + PCI_EXP_DEVCAP, ®16);
> if (reg16 & PCI_EXP_DEVCAP_FLR)
> dev->has_flr = 1;
> }
>
> static void quirk_no_flr(...)
> {
> dev->has_flr = 0; # get rid of PCI_DEV_FLAGS_NO_FLR_RESET
> }
>
> int pcie_flr(...)
> {
> if (!dev->has_flr)
> return -ENOTTY;
>
> if (!pci_wait_for_pending_transaction(dev))
> ...
> }
>
> I think this should be enough that we could get rid of pcie_has_flr()
> without having to expose the "probe" argument outside drivers/pci/.
>
> Procedural note: if we *do* have to expose the "probe" argument, can
> you arrange it to have the correct type before touching the drivers, so
> we only have to touch the drivers once?
>
Thanks for the details. I'll add dev->has_flr check in pcie_reset_flr.
[...]
Thanks,
Amey
next prev parent reply other threads:[~2021-06-18 16:32 UTC|newest]
Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-08 5:48 [PATCH v7 0/8] Expose and manage PCI device reset Amey Narkhede
2021-06-08 5:48 ` [PATCH v7 1/8] PCI: Add pcie_reset_flr to follow calling convention of other reset methods Amey Narkhede
2021-06-10 20:15 ` Shanker R Donthineni
2021-06-17 21:57 ` Bjorn Helgaas
2021-06-17 22:51 ` Alex Williamson
2021-06-18 16:32 ` Amey Narkhede [this message]
2021-06-24 12:23 ` Bjorn Helgaas
2021-06-24 15:28 ` Amey Narkhede
2021-06-24 16:15 ` Bjorn Helgaas
2021-06-24 18:48 ` Alex Williamson
2021-06-08 5:48 ` [PATCH v7 2/8] PCI: Add new array for keeping track of ordering of " Amey Narkhede
2021-06-10 20:15 ` Shanker R Donthineni
2021-06-17 23:13 ` Bjorn Helgaas
2021-06-18 17:22 ` Amey Narkhede
2021-06-21 15:02 ` Shanker R Donthineni
2021-06-21 17:15 ` Amey Narkhede
2021-06-21 18:37 ` Bjorn Helgaas
2021-06-08 5:48 ` [PATCH v7 3/8] PCI: Remove reset_fn field from pci_dev Amey Narkhede
2021-06-10 20:16 ` Shanker R Donthineni
2021-06-08 5:48 ` [PATCH v7 4/8] PCI/sysfs: Allow userspace to query and set device reset mechanism Amey Narkhede
2021-06-09 21:57 ` Raphael Norwitz
2021-06-09 22:36 ` Shanker R Donthineni
2021-06-09 22:48 ` Raphael Norwitz
2021-06-10 20:16 ` Shanker R Donthineni
2021-06-18 20:00 ` Bjorn Helgaas
2021-06-19 13:59 ` Amey Narkhede
2021-06-21 13:01 ` Bjorn Helgaas
2021-06-21 17:28 ` Amey Narkhede
2021-06-21 19:07 ` Bjorn Helgaas
2021-06-21 19:33 ` Amey Narkhede
2021-06-23 12:06 ` Bjorn Helgaas
2021-06-23 14:07 ` Amey Narkhede
2021-06-23 17:56 ` Amey Narkhede
2021-06-23 17:21 ` Alex Williamson
2021-06-24 12:15 ` Bjorn Helgaas
2021-06-24 15:12 ` Amey Narkhede
2021-06-24 16:56 ` Bjorn Helgaas
2021-06-24 17:20 ` Shanker R Donthineni
2021-06-24 17:28 ` Amey Narkhede
2021-06-24 17:59 ` Bjorn Helgaas
2021-06-08 5:48 ` [PATCH v7 5/8] PCI: Setup ACPI_COMPANION early Amey Narkhede
2021-06-08 5:48 ` [PATCH v7 6/8] PCI: Add support for ACPI _RST reset method Amey Narkhede
2021-06-08 5:48 ` [PATCH v7 7/8] PCI: Enable NO_BUS_RESET quirk for Nvidia GPUs Amey Narkhede
2021-06-10 23:16 ` Bjorn Helgaas
2021-06-10 23:33 ` Shanker R Donthineni
2021-06-10 23:43 ` Shanker R Donthineni
2021-06-10 23:53 ` Bjorn Helgaas
2021-06-11 4:15 ` Shanker R Donthineni
2021-06-08 5:48 ` [PATCH v7 8/8] PCI: Change the type of probe argument in reset functions Amey Narkhede
2021-06-09 21:40 ` Raphael Norwitz
2021-06-08 10:05 ` [PATCH v7 0/8] Expose and manage PCI device reset Enrico Weigelt, metux IT consult
2021-06-08 15:44 ` Amey Narkhede
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20210618163223.otdhrkxnyng32okp@archlinux \
--to=ameynarkhede03@gmail.com \
--cc=alex.williamson@redhat.com \
--cc=hch@lst.de \
--cc=helgaas@kernel.org \
--cc=kw@linux.com \
--cc=lenb@kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=okaya@kernel.org \
--cc=raphael.norwitz@nutanix.com \
--cc=rjw@rjwysocki.net \
--cc=sdonthineni@nvidia.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).