From: Lizhi Hou <lizhi.hou@xilinx.com>
To: <linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>,
<robh@kernel.org>
Cc: Lizhi Hou <lizhi.hou@xilinx.com>, <yilun.xu@intel.com>,
<maxz@xilinx.com>, <sonal.santan@xilinx.com>, <yliu@xilinx.com>,
<michal.simek@xilinx.com>, <stefanos@xilinx.com>,
<trix@redhat.com>, <mdf@kernel.org>, <dwmw2@infradead.org>,
<linux-kernel@vger.kernel.org>, Max Zhen <max.zhen@xilinx.com>
Subject: [PATCH V1 RESEND 2/4] Documentation: devicetree: bindings: add binding for PCIe endpoint bus
Date: Fri, 4 Mar 2022 21:23:02 -0800 [thread overview]
Message-ID: <20220305052304.726050-3-lizhi.hou@xilinx.com> (raw)
In-Reply-To: <20220305052304.726050-1-lizhi.hou@xilinx.com>
Create device tree binding document for PCIe endpoint bus.
Signed-off-by: Sonal Santan <sonal.santan@xilinx.com>
Signed-off-by: Max Zhen <max.zhen@xilinx.com>
Signed-off-by: Lizhi Hou <lizhi.hou@xilinx.com>
---
.../devicetree/bindings/bus/pci-ep-bus.yaml | 72 +++++++++++++++++++
1 file changed, 72 insertions(+)
create mode 100644 Documentation/devicetree/bindings/bus/pci-ep-bus.yaml
diff --git a/Documentation/devicetree/bindings/bus/pci-ep-bus.yaml b/Documentation/devicetree/bindings/bus/pci-ep-bus.yaml
new file mode 100644
index 000000000000..0ca96298db6f
--- /dev/null
+++ b/Documentation/devicetree/bindings/bus/pci-ep-bus.yaml
@@ -0,0 +1,72 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/bus/pci-ep-bus.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: PCIe Endpoint Bus binding
+
+description: |
+ PCIe device may use flattened device tree to describe apertures in its
+ PCIe BARs. The Bus PCIe endpoint node is created and attached under the
+ device tree root node for this kind of device. Then the flatten device
+ tree overlay for this device is attached under the endpoint node.
+
+ The aperture address which is under the endpoint node consists of BAR
+ index and offset. It uses the following encoding:
+
+ 0xIooooooo 0xoooooooo
+
+ Where:
+
+ I = BAR index
+ oooooo oooooooo = BAR offset
+
+ The endpoint is compatible with 'simple-bus' and contains 'ranges'
+ property for translating aperture address to CPU address.
+
+allOf:
+ - $ref: /schemas/simple-bus.yaml#
+
+maintainers:
+ - Lizhi Hou <lizhi.hou@xilinx.com>
+
+properties:
+ compatible:
+ contains:
+ const: pci-ep-bus
+
+ "#address-cells":
+ const: 2
+
+ "#size-cells":
+ const: 2
+
+ ranges: true
+
+patternProperties:
+ "^.*@[0-9a-f]+$":
+ description: hardware apertures belong to this device.
+ type: object
+
+required:
+ - compatible
+ - "#address-cells"
+ - "#size-cells"
+ - ranges
+
+additionalProperties: false
+
+examples:
+ - |
+ bus {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ pci-ep-bus@e0000000 {
+ compatible = "pci-ep-bus", "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x0 0x0 0xe0000000 0x0 0x2000000
+ 0x20000000 0x0 0x0 0xe4200000 0x0 0x40000>;
+ };
+ };
--
2.27.0
next prev parent reply other threads:[~2022-03-05 5:23 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-05 5:23 [PATCH V1 RESEND 0/4] Infrastructure to define apertures in a PCIe device with a flattened device tree Lizhi Hou
2022-03-05 5:23 ` [PATCH V1 RESEND 1/4] pci: add interface to create pci-ep device tree node Lizhi Hou
2022-03-10 10:02 ` Dan Carpenter
2022-03-10 19:34 ` Bjorn Helgaas
2022-06-21 15:12 ` Manivannan Sadhasivam
2022-03-05 5:23 ` Lizhi Hou [this message]
2022-03-06 15:37 ` [PATCH V1 RESEND 2/4] Documentation: devicetree: bindings: add binding for PCIe endpoint bus Tom Rix
2022-03-07 14:07 ` Rob Herring
2022-04-22 21:57 ` Lizhi Hou
2022-05-13 15:19 ` Lizhi Hou
2022-06-21 15:06 ` Manivannan Sadhasivam
2022-03-05 5:23 ` [PATCH V1 RESEND 3/4] fpga: xrt: management physical function driver Lizhi Hou
2022-06-21 15:16 ` Manivannan Sadhasivam
2023-06-30 16:38 ` Bjorn Helgaas
2022-03-05 5:23 ` [PATCH V1 RESEND 4/4] of: enhance overlay applying interface to specific target base node Lizhi Hou
2022-03-10 20:07 ` Rob Herring
2022-03-10 19:27 ` [PATCH V1 RESEND 0/4] Infrastructure to define apertures in a PCIe device with a flattened device tree Bjorn Helgaas
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