From: Herve Codina <herve.codina@bootlin.com>
To: "Marek Vasut" <marek.vasut+renesas@gmail.com>,
"Yoshihiro Shimoda" <yoshihiro.shimoda.uh@renesas.com>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Rob Herring" <robh+dt@kernel.org>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Geert Uytterhoeven" <geert+renesas@glider.be>,
"Magnus Damm" <magnus.damm@gmail.com>,
"Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
"Krzysztof Wilczyński" <kw@linux.com>
Cc: Rob Herring <robh@kernel.org>,
linux-pci@vger.kernel.org, linux-renesas-soc@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Sergey Shtylyov <s.shtylyov@omp.ru>,
Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
Clement Leger <clement.leger@bootlin.com>,
Miquel Raynal <miquel.raynal@bootlin.com>,
Herve Codina <herve.codina@bootlin.com>
Subject: [PATCH v5 4/6] ARM: dts: r9a06g032: Add internal PCI bridge node
Date: Fri, 29 Apr 2022 15:41:41 +0200 [thread overview]
Message-ID: <20220429134143.628428-6-herve.codina@bootlin.com> (raw)
In-Reply-To: <20220429134143.628428-1-herve.codina@bootlin.com>
Add the device node for the r9a06g032 internal PCI bridge device.
Signed-off-by: Herve Codina <herve.codina@bootlin.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
arch/arm/boot/dts/r9a06g032.dtsi | 29 +++++++++++++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi
index 20286433d3c6..45944f849190 100644
--- a/arch/arm/boot/dts/r9a06g032.dtsi
+++ b/arch/arm/boot/dts/r9a06g032.dtsi
@@ -94,6 +94,35 @@ sysctrl: system-controller@4000c000 {
clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext";
};
+ pci_usb: pci@40030000 {
+ compatible = "renesas,pci-r9a06g032", "renesas,pci-rzn1";
+ device_type = "pci";
+ clocks = <&sysctrl R9A06G032_HCLK_USBH>,
+ <&sysctrl R9A06G032_HCLK_USBPM>,
+ <&sysctrl R9A06G032_CLK_PCI_USB>;
+ clock-names = "hclkh", "hclkpm", "pciclk";
+ power-domains = <&sysctrl>;
+ reg = <0x40030000 0xc00>,
+ <0x40020000 0x1100>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+
+ bus-range = <0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges = <0x02000000 0 0x40020000 0x40020000 0 0x00010000>;
+ /* Should map all possible DDR as inbound ranges, but
+ * the IP only supports a 256MB, 512MB, or 1GB window.
+ * flags, PCI addr (64-bit), CPU addr, PCI size (64-bit)
+ */
+ dma-ranges = <0x42000000 0 0x80000000 0x80000000 0 0x40000000>;
+ interrupt-map-mask = <0xf800 0 0 0x7>;
+ interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH
+ 0x0800 0 0 1 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH
+ 0x1000 0 0 2 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
uart0: serial@40060000 {
compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart";
reg = <0x40060000 0x400>;
--
2.35.1
next prev parent reply other threads:[~2022-04-29 13:42 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-29 13:41 [PATCH v5 0/6] RZN1 USB Host support Herve Codina
2022-04-29 13:41 ` [PATCH v4 " Herve Codina
2022-04-29 13:41 ` [PATCH v5 1/6] dt-bindings: PCI: pci-rcar-gen2: Convert bindings to json-schema Herve Codina
2022-04-29 13:41 ` [PATCH v5 2/6] dt-bindings: PCI: renesas,pci-rcar-gen2: Add device tree support for r9a06g032 Herve Codina
2022-05-01 8:51 ` Krzysztof Kozlowski
2022-05-02 9:19 ` Geert Uytterhoeven
2022-05-02 19:44 ` Rob Herring
2022-05-03 6:51 ` Geert Uytterhoeven
2022-05-03 9:29 ` Krzysztof Kozlowski
2022-05-03 9:37 ` Geert Uytterhoeven
2022-05-06 12:35 ` Herve Codina
2022-05-04 13:53 ` Rob Herring
2022-05-20 8:23 ` Herve Codina
2022-05-20 8:29 ` Geert Uytterhoeven
2022-05-20 8:31 ` Krzysztof Kozlowski
2022-04-29 13:41 ` [PATCH v5 3/6] PCI: rcar-gen2: Add RZ/N1 SOCs family compatible string Herve Codina
2022-05-11 9:42 ` Lorenzo Pieralisi
2022-05-11 12:05 ` Geert Uytterhoeven
2022-04-29 13:41 ` Herve Codina [this message]
2022-04-29 13:41 ` [PATCH v5 5/6] ARM: dts: r9a06g032: Add USB PHY DT support Herve Codina
2022-04-29 13:41 ` [PATCH v5 6/6] ARM: dts: r9a06g032: Link the PCI USB devices to the USB PHY Herve Codina
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