From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
To: Andy Gross <agross@kernel.org>,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzk@kernel.org>,
Jingoo Han <jingoohan1@gmail.com>,
Gustavo Pimentel <gustavo.pimentel@synopsys.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Bjorn Helgaas <bhelgaas@google.com>,
Stanimir Varbanov <svarbanov@mm-sol.com>,
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Vinod Koul <vkoul@kernel.org>,
linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org,
devicetree@vger.kernel.org,
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Subject: [PATCH v6 6/7] dt-bindings: PCI: qcom: Support additional MSI interrupts
Date: Thu, 5 May 2022 12:12:30 +0300 [thread overview]
Message-ID: <20220505091231.1308963-7-dmitry.baryshkov@linaro.org> (raw)
In-Reply-To: <20220505091231.1308963-1-dmitry.baryshkov@linaro.org>
On Qualcomm platforms each group of 32 MSI vectors is routed to the
separate GIC interrupt. Document mapping of additional interrupts.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../devicetree/bindings/pci/qcom,pcie.yaml | 45 ++++++++++++++++++-
1 file changed, 44 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
index 0b69b12b849e..fd3290e0e220 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
@@ -43,11 +43,20 @@ properties:
maxItems: 5
interrupts:
- maxItems: 1
+ minItems: 1
+ maxItems: 8
interrupt-names:
+ minItems: 1
items:
- const: msi
+ - const: msi2
+ - const: msi3
+ - const: msi4
+ - const: msi5
+ - const: msi6
+ - const: msi7
+ - const: msi8
# Common definitions for clocks, clock-names and reset.
# Platform constraints are described later.
@@ -623,6 +632,40 @@ allOf:
- resets
- reset-names
+ # On newer chipsets support either 1 or 8 msi interrupts
+ # On older chipsets it's always 1 msi interrupt
+ - if:
+ properties:
+ compatibles:
+ contains:
+ enum:
+ - qcom,pcie-msm8996
+ - qcom,pcie-sc7280
+ - qcom,pcie-sc8180x
+ - qcom,pcie-sdm845
+ - qcom,pcie-sm8150
+ - qcom,pcie-sm8250
+ - qcom,pcie-sm8450-pcie0
+ - qcom,pcie-sm8450-pcie1
+ then:
+ oneOf:
+ - properties:
+ interrupts:
+ maxItems: 1
+ interrupt-names:
+ maxItems: 1
+ - properties:
+ interrupts:
+ minItems: 8
+ interrupt-names:
+ minItems: 8
+ else:
+ properties:
+ interrupts:
+ maxItems: 1
+ interrupt-names:
+ maxItems: 1
+
unevaluatedProperties: false
examples:
--
2.35.1
next prev parent reply other threads:[~2022-05-05 9:12 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-05 9:12 [PATCH v6 0/7] PCI: qcom: Fix higher MSI vectors handling Dmitry Baryshkov
2022-05-05 9:12 ` [PATCH v6 1/7] PCI: qcom: Revert "PCI: qcom: Add support for handling MSIs from 8 endpoints" Dmitry Baryshkov
2022-05-05 9:12 ` [PATCH v6 2/7] PCI: dwc: Correct msi_irq condition in dw_pcie_free_msi() Dmitry Baryshkov
2022-05-05 9:12 ` [PATCH v6 3/7] PCI: dwc: Add msi_host_deinit callback Dmitry Baryshkov
2022-05-05 9:12 ` [PATCH v6 4/7] PCI: dwc: Export several functions useful for MSI implentations Dmitry Baryshkov
2022-05-05 9:37 ` Stanimir Varbanov
2022-05-05 9:12 ` [PATCH v6 5/7] PCI: qcom: Handle MSIs routed to multiple GIC interrupts Dmitry Baryshkov
2022-05-05 9:49 ` Stanimir Varbanov
2022-05-05 9:12 ` Dmitry Baryshkov [this message]
2022-05-05 9:12 ` [PATCH v6 7/7] arm64: dts: qcom: sm8250: provide additional MSI interrupts Dmitry Baryshkov
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