From: Serge Semin <Sergey.Semin@baikalelectronics.ru>
To: Rob Herring <robh@kernel.org>,
Bjorn Helgaas <bhelgaas@google.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Jingoo Han <jingoohan1@gmail.com>,
Gustavo Pimentel <gustavo.pimentel@synopsys.com>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Alim Akhtar <alim.akhtar@samsung.com>,
Kunihiko Hayashi <hayashi.kunihiko@socionext.com>,
Masami Hiramatsu <mhiramat@kernel.org>,
Marek Szyprowski <m.szyprowski@samsung.com>,
Jaehoon Chung <jh80.chung@samsung.com>
Cc: "Serge Semin" <Sergey.Semin@baikalelectronics.ru>,
"Serge Semin" <fancer.lancer@gmail.com>,
"Alexey Malahov" <Alexey.Malahov@baikalelectronics.ru>,
"Pavel Parkhomenko" <Pavel.Parkhomenko@baikalelectronics.ru>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Frank Li" <Frank.Li@nxp.com>,
"Manivannan Sadhasivam" <manivannan.sadhasivam@linaro.org>,
linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-samsung-soc@vger.kernel.org
Subject: [PATCH v3 09/17] dt-bindings: PCI: dwc: Add clocks/resets common properties
Date: Fri, 10 Jun 2022 11:56:57 +0300 [thread overview]
Message-ID: <20220610085706.15741-10-Sergey.Semin@baikalelectronics.ru> (raw)
In-Reply-To: <20220610085706.15741-1-Sergey.Semin@baikalelectronics.ru>
DW PCIe RP/EP reference manuals explicit define all the clocks and reset
requirements in [1] and [2]. Seeing the DW PCIe vendor-specific
DT-bindings have already started assigning random names to the same set of
the clocks and resets lines, let's define a generic names sets and add
them to the DW PCIe definitions in the common DT-schema. These definitions
will be used in the generic DW PCIe DT-schema and can be referenced in the
particular DW PCIe DT-bindings if they are compatible with them, otherwise
the platforms can be left with already defined clocks/resets properties.
[1] Synopsys DesignWare Cores PCI Express Controller Databook - DWC PCIe
Root Port, Version 5.40a, March 2019, p.55 - 78.
[2] Synopsys DesignWare Cores PCI Express Controller Databook - DWC PCIe
Endpoint, Version 5.40a, March 2019, p.58 - 81.
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
---
Changelog v3:
- This is a new patch unpinned from the next one:
https://lore.kernel.org/linux-pci/20220503214638.1895-2-Sergey.Semin@baikalelectronics.ru/
by the Rob' request. (@Rob)
- Drop synonymous from the names list since the device schemas create
their own enumerations anyway.
---
.../bindings/pci/samsung,exynos-pcie.yaml | 3 +-
.../bindings/pci/snps,dw-pcie-common.yaml | 100 ++++++++++++++++++
.../bindings/pci/snps,dw-pcie-ep.yaml | 26 +++++
.../devicetree/bindings/pci/snps,dw-pcie.yaml | 20 +++-
.../pci/socionext,uniphier-pcie-ep.yaml | 3 +-
5 files changed, 149 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml b/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml
index 445eed94b53f..fedb774938f4 100644
--- a/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml
@@ -16,7 +16,8 @@ description: |+
snps,dw-pcie.yaml.
allOf:
- - $ref: /schemas/pci/snps,dw-pcie.yaml#
+ - $ref: /schemas/pci/pci-bus.yaml#
+ - $ref: /schemas/pci/snps,dw-pcie-common.yaml#
properties:
compatible:
diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml
index c6a55f90ddd5..f22fb01c9bd0 100644
--- a/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml
+++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml
@@ -58,6 +58,36 @@ properties:
minItems: 1
maxItems: 26
+ clocks:
+ description:
+ DWC PCIe reference manual explicitly defines a set of the clocks required
+ to get the controller working correctly. In general all of them can
+ be divided into two groups':' application and core clocks. Note the
+ platforms may have some of the clock sources unspecified in case if the
+ corresponding domains are fed up from a common clock source.
+ minItems: 1
+ maxItems: 7
+
+ clock-names:
+ minItems: 1
+ maxItems: 7
+
+ resets:
+ description:
+ DWC PCIe reference manual explicitly defines a set of the reset
+ signals required to be de-asserted to properly activate the controller
+ sub-parts. All of these signals can be divided into two sub-groups':'
+ application and core resets with respect to the main sub-domains they
+ are supposed to reset. Note the platforms may have some of these signals
+ unspecified in case if they are automatically handled or aggregated into
+ a comprehensive control module.
+ minItems: 1
+ maxItems: 10
+
+ reset-names:
+ minItems: 1
+ maxItems: 10
+
phys:
description:
There can be up to the number of possible lanes PHYs specified.
@@ -218,4 +248,74 @@ definitions:
uncorrectable error.
const: sft_ue
+ clock-names:
+ description:
+ Reference clock names common for the DWC PCIe Root Port and Endpoint
+ controllers.
+ anyOf:
+ - description:
+ Data Bus Interface (DBI) clock. Clock signal for the AXI-bus
+ interface of the Configuration-Dependent Module, which is
+ basically the set of the controller CSRs.
+ const: dbi
+ - description:
+ Application AXI-bus Master interface clock. Basically this is
+ a clock for the controller DMA interface (PCI-to-CPU).
+ const: mstr
+ - description:
+ Application AXI-bus Slave interface clock. This is a clock for
+ the CPU-to-PCI memory IO interface.
+ const: slv
+ - description:
+ Controller Core-PCS PIPE interface clock. It's normally
+ supplied by an external PCS-PHY.
+ const: pipe
+ - description:
+ Controller Primary clock. It's assumed that all controller input
+ signals (except resets) are synchronous to this clock.
+ const: core
+ - description:
+ Auxiliary clock for the controller PMC domain. The controller
+ partitioning implies having some parts to operate with this
+ clock in some power management states.
+ const: aux
+ - description:
+ Generic reference clock. In case if there are several
+ interfaces fed up with a common clock source it's advisable to
+ define it with this name (for instance pipe, core and aux can
+ be connected to a single source of the periodic signal).
+ const: ref
+ - description:
+ Clock for the PHY registers interface. Originally this is
+ a PHY-viewport-based interface, but some platform may have
+ specifically designed one.
+ const: phy_reg
+
+ reset-names:
+ description:
+ Reset signal names common for the DWC PCIe Root Port and Endpoint
+ controllers.
+ anyOf:
+ - description: Data Bus Interface (DBI) domain reset
+ const: dbi
+ - description: AXI-bus Master interface reset
+ const: mstr
+ - description: AXI-bus Slave interface reset
+ const: slv
+ - description: Controller Non-sticky CSR flags reset
+ const: non-sticky
+ - description: Controller sticky CSR flags reset
+ const: sticky
+ - description: PIPE-interface (Core-PCS) logic reset
+ const: pipe
+ - description:
+ Controller primary reset (resets everything except PMC module)
+ const: core
+ - description: PCS/PHY block reset
+ const: phy
+ - description: PMC hot reset signal
+ const: hot
+ - description: Cold reset signal
+ const: pwr
+
...
diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml
index bfff723b529d..bb7e4381d392 100644
--- a/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml
+++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml
@@ -74,6 +74,26 @@ properties:
items:
$ref: /schemas/pci/snps,dw-pcie-common.yaml#/definitions/interrupt-names
+ clocks:
+ minItems: 1
+ maxItems: 7
+
+ clock-names:
+ minItems: 1
+ maxItems: 7
+ items:
+ $ref: /schemas/pci/snps,dw-pcie-common.yaml#/definitions/clock-names
+
+ resets:
+ minItems: 1
+ maxItems: 10
+
+ reset-names:
+ minItems: 1
+ maxItems: 10
+ items:
+ $ref: /schemas/pci/snps,dw-pcie-common.yaml#/definitions/reset-names
+
max-functions:
maximum: 32
@@ -109,6 +129,12 @@ examples:
interrupts = <23>, <24>;
interrupt-names = "dma0", "dma1";
+ clocks = <&sys_clk 12>, <&sys_clk 24>;
+ clock-names = "dbi", "ref";
+
+ resets = <&sys_rst 12>, <&sys_rst 24>;
+ reset-names = "dbi", "phy";
+
phys = <&pcie_phy0>, <&pcie_phy1>, <&pcie_phy2>, <&pcie_phy3>;
phy-names = "pcie0", "pcie1", "pcie2", "pcie3";
diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
index 9e96c6d0ef48..518fa5626c11 100644
--- a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
@@ -78,7 +78,25 @@ properties:
- contains:
const: msi
- clocks: true
+ clocks:
+ minItems: 1
+ maxItems: 7
+
+ clock-names:
+ minItems: 1
+ maxItems: 7
+ items:
+ $ref: /schemas/pci/snps,dw-pcie-common.yaml#/definitions/clock-names
+
+ resets:
+ minItems: 1
+ maxItems: 10
+
+ reset-names:
+ minItems: 1
+ maxItems: 10
+ items:
+ $ref: /schemas/pci/snps,dw-pcie-common.yaml#/definitions/reset-names
additionalProperties: true
diff --git a/Documentation/devicetree/bindings/pci/socionext,uniphier-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/socionext,uniphier-pcie-ep.yaml
index 1719a36952c0..8c2a8e8f96f9 100644
--- a/Documentation/devicetree/bindings/pci/socionext,uniphier-pcie-ep.yaml
+++ b/Documentation/devicetree/bindings/pci/socionext,uniphier-pcie-ep.yaml
@@ -16,7 +16,8 @@ maintainers:
- Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
allOf:
- - $ref: /schemas/pci/snps,dw-pcie-ep.yaml#
+ - $ref: /schemas/pci/pci-ep.yaml#
+ - $ref: /schemas/pci/snps,dw-pcie-common.yaml#
properties:
compatible:
--
2.35.1
next prev parent reply other threads:[~2022-06-10 9:05 UTC|newest]
Thread overview: 51+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-10 8:56 [PATCH v3 00/17] PCI: dwc: Add generic resources and Baikal-T1 support Serge Semin
2022-06-10 8:56 ` [PATCH v3 01/17] dt-bindings: PCI: dwc: Detach common RP/EP DT bindings Serge Semin
2022-06-10 8:56 ` [PATCH v3 02/17] dt-bindings: PCI: dwc: Remove bus node from the examples Serge Semin
2022-06-15 16:30 ` Rob Herring
2022-06-10 8:56 ` [PATCH v3 03/17] dt-bindings: PCI: dwc: Add phys/phy-names common properties Serge Semin
2022-06-10 8:56 ` [PATCH v3 04/17] dt-bindings: PCI: dwc: Add max-link-speed common property Serge Semin
2022-06-15 14:55 ` Rob Herring
2022-06-19 14:27 ` Serge Semin
2022-06-28 12:15 ` Serge Semin
2022-06-28 14:56 ` Rob Herring
2022-06-29 1:50 ` Serge Semin
2022-07-01 14:44 ` Rob Herring
2022-07-07 19:02 ` Serge Semin
2022-06-10 8:56 ` [PATCH v3 05/17] dt-bindings: PCI: dwc: Stop selecting generic bindings by default Serge Semin
2022-06-10 8:56 ` [PATCH v3 06/17] dt-bindings: PCI: dwc: Add max-functions EP property Serge Semin
2022-06-15 16:31 ` Rob Herring
2022-06-10 8:56 ` [PATCH v3 07/17] dt-bindings: PCI: dwc: Add interrupts/interrupt-names common properties Serge Semin
2022-06-15 15:32 ` Rob Herring
2022-06-19 16:37 ` Serge Semin
2022-06-28 12:18 ` Serge Semin
2022-07-07 19:25 ` Serge Semin
2022-06-10 8:56 ` [PATCH v3 08/17] dt-bindings: PCI: dwc: Add reg/reg-names " Serge Semin
2022-06-10 8:56 ` Serge Semin [this message]
2022-06-10 8:56 ` [PATCH v3 10/17] dt-bindings: PCI: dwc: Add dma-coherent property Serge Semin
2022-06-10 8:56 ` [PATCH v3 11/17] dt-bindings: PCI: dwc: Apply common schema to Rockchip DW PCIe nodes Serge Semin
2022-06-10 13:12 ` Rob Herring
2022-06-10 21:13 ` Serge Semin
2022-06-10 8:57 ` [PATCH v3 12/17] dt-bindings: PCI: dwc: Add Baikal-T1 PCIe Root Port bindings Serge Semin
2022-06-15 16:37 ` Rob Herring
2022-06-19 20:03 ` Serge Semin
2022-06-28 12:19 ` Serge Semin
2022-07-01 14:59 ` Rob Herring
2022-07-07 19:19 ` Serge Semin
2022-06-10 8:57 ` [PATCH v3 13/17] PCI: dwc: Introduce generic controller capabilities interface Serge Semin
2022-06-15 16:42 ` Rob Herring
2022-06-10 8:57 ` [PATCH v3 14/17] PCI: dwc: Introduce generic resources getter Serge Semin
2022-06-15 16:46 ` Rob Herring
2022-06-10 8:57 ` [PATCH v3 15/17] PCI: dwc: Combine iATU detection procedures Serge Semin
2022-06-15 16:47 ` Rob Herring
2022-06-10 8:57 ` [PATCH v3 16/17] PCI: dwc: Introduce generic platform clocks and resets Serge Semin
2022-06-10 8:57 ` [PATCH v3 17/17] PCI: dwc: Add Baikal-T1 PCIe controller support Serge Semin
2022-06-15 16:48 ` Bjorn Helgaas
2022-06-20 17:13 ` Serge Semin
2022-06-21 18:29 ` Bjorn Helgaas
2022-06-22 17:04 ` Serge Semin
2022-06-28 12:23 ` Serge Semin
2022-06-28 15:17 ` Bjorn Helgaas
2022-06-15 17:10 ` Rob Herring
2022-06-19 20:39 ` Serge Semin
2022-07-12 20:29 ` Rob Herring
2022-07-12 20:58 ` Serge Semin
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20220610085706.15741-10-Sergey.Semin@baikalelectronics.ru \
--to=sergey.semin@baikalelectronics.ru \
--cc=Alexey.Malahov@baikalelectronics.ru \
--cc=Frank.Li@nxp.com \
--cc=Pavel.Parkhomenko@baikalelectronics.ru \
--cc=alim.akhtar@samsung.com \
--cc=bhelgaas@google.com \
--cc=devicetree@vger.kernel.org \
--cc=fancer.lancer@gmail.com \
--cc=gustavo.pimentel@synopsys.com \
--cc=hayashi.kunihiko@socionext.com \
--cc=jh80.chung@samsung.com \
--cc=jingoohan1@gmail.com \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=kw@linux.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=linux-samsung-soc@vger.kernel.org \
--cc=lorenzo.pieralisi@arm.com \
--cc=m.szyprowski@samsung.com \
--cc=manivannan.sadhasivam@linaro.org \
--cc=mhiramat@kernel.org \
--cc=robh+dt@kernel.org \
--cc=robh@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).