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Tue, 14 Jun 2022 10:29:16 +0900 (KST) Mime-Version: 1.0 Subject: [PATCH v3 2/5] dt-bindings: phy: Add ARTPEC-8 PCIe phy Reply-To: wangseok.lee@samsung.com Sender: Wangseok Lee From: Wangseok Lee To: "robh+dt@kernel.org" , "krzk+dt@kernel.org" , "kishon@ti.com" , "vkoul@kernel.org" , "linux-kernel@vger.kernel.org" , "jesper.nilsson@axis.com" , "lars.persson@axis.com" , "bhelgaas@google.com" , "linux-phy@lists.infradead.org" , "linux-pci@vger.kernel.org" , "devicetree@vger.kernel.org" , "lorenzo.pieralisi@arm.com" , "kw@linux.com" , "linux-arm-kernel@axis.com" , "kernel@axis.com" CC: Moon-Ki Jun , Sang Min Kim , Dongjin Yang , Yeeun Kim X-Priority: 3 X-Content-Kind-Code: NORMAL In-Reply-To: <20220614011616epcms2p7dcaa67c53b7df5802dd7a697e2d472d7@epcms2p7> X-CPGS-Detection: blocking_info_exchange X-Drm-Type: N,general X-Msg-Generator: Mail X-Msg-Type: PERSONAL X-Reply-Demand: N Message-ID: <20220614012916epcms2p5cf8d55e7420dea10bb4a05d91aaf99dd@epcms2p5> Date: Tue, 14 Jun 2022 10:29:16 +0900 X-CMS-MailID: 20220614012916epcms2p5cf8d55e7420dea10bb4a05d91aaf99dd Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: AUTO_CONFIDENTIAL X-CPGSPASS: Y X-CPGSPASS: Y CMS-TYPE: 102P X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrMJsWRmVeSWpSXmKPExsWy7bCmuW7Ok+VJBofbzCyWNGVYvDykaTH/ yDlWi90zljNZzJx6htni+aFZzBafWlQtLjztYbN4Oesem0VDz29WiyNvPjJb7D++ksni8q45 bBZn5x1ns5iw6huLxZvfL9gtzi3OtGjde4TdYuedE8wWv7b+YXIQ8Vgzbw2jx/V1AR4LNpV6 bFrVyebx5Mp0Jo/NS+o9+rasYvQ4fmM7k8fnTXIBnFHZNhmpiSmpRQqpecn5KZl56bZK3sHx zvGmZgaGuoaWFuZKCnmJuam2Si4+AbpumTlATykplCXmlAKFAhKLi5X07WyK8ktLUhUy8otL bJVSC1JyCswL9IoTc4tL89L18lJLrAwNDIxMgQoTsjP2LFzIVtAnWvHj7lWWBsZ2gS5GTg4J AROJTX3rmLsYuTiEBHYwSvyceJexi5GDg1dAUOLvDmGQGmEBe4kJzVeZQWwhASWJHWvmMUPE 9SWur+hmBbHZBHQl/i1+yQZiiwh8ZpW4vkcQZCazwAJGif2/9zFCLOOVmNH+lAXClpbYvnwr WJxTwE9i4dFJTBBxDYkfy3qZIWxRiZur37LD2O+PzYeaIyLReu8sVI2gxIOfu6HiUhILnhxi hbCrJfb//Q01s4FRov9+KshfEkBH77huDBLmFfCV2HX8Mth4FgFViW/dXVCrXCSatl0DG8ks IC+x/e0cZpBWZgFNifW79CGmKEscucUC81TDxt/s6GxmAT6JjsN/4eI75j2BOkZNYt7KncwT GJVnIcJ5FpJdsxB2LWBkXsUollpQnJueWmxUYAKP2uT83E2M4NSt5bGDcfbbD3qHGJk4GA8x SnAwK4nwTr64LEmINyWxsiq1KD++qDQntfgQoynQlxOZpUST84HZI68k3tDE0sDEzMzQ3MjU wFxJnNcrZUOikEB6YklqdmpqQWoRTB8TB6dUA1P0o608P14ea47vOuBlqFXj/702XO7b87dF tS1bk6sy/37I7pfXqeydJJtQsGWe92a/PUl775mXXNRxbt5qo3NQ9X2+UfTLmCvbOtONNjJv m6x+WIC18c/Eimnm3376KMebrbPlmvuFKeHipv7vy7qv5F0/XORaNlvvw/G7raH/cmbPXiEv Eb7q0Z5368vOiknE5rktrhec/XnbQabU+BU/Fa14z7gdnlC772hS9lEOsUNWciVR+76v35Mz 23dqM7/Z7tUy/qHGWqbWdnovPau/bTTP4dXqP3B349R3/2wD4wVmKb7purZT6sXF8uhqpikP pK+xuxa4lhduavpfU7Bp/6S/q+ZWLjYTrc3ONldiKc5INNRiLipOBABzDfAlZgQAAA== DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20220614011616epcms2p7dcaa67c53b7df5802dd7a697e2d472d7 References: <20220614011616epcms2p7dcaa67c53b7df5802dd7a697e2d472d7@epcms2p7> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add description to support Axis, ARTPEC-8 SoC. ARTPEC-8 is the SoC platform of Axis Communications and PCIe phy is designed based on SAMSUNG PHY. Signed-off-by: Wangseok Lee --- v2->v3 : -modify version history to fit the linux commit rule -remove 'Device Tree Bindings' on title -remove clock-names entries -change node name to soc from artpec8 on excamples v1->v2 : -'make dt_binding_check' result improvement -Add the missing property list -Align the indentation of continued lines/entries --- .../bindings/phy/axis,artpec8-pcie-phy.yaml | 73 ++++++++++++++++++++++ 1 file changed, 73 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/axis,artpec8-pcie-phy.yaml diff --git a/Documentation/devicetree/bindings/phy/axis,artpec8-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/axis,artpec8-pcie-phy.yaml new file mode 100644 index 0000000..316b774 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/axis,artpec8-pcie-phy.yaml @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/axis,artpec8-pcie-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARTPEC-8 SoC PCIe PHY + +maintainers: + - Jesper Nilsson + +properties: + compatible: + const: axis,artpec8-pcie-phy + + reg: + items: + - description: PHY registers. + - description: PHY coding sublayer registers. + + reg-names: + items: + - const: phy + - const: pcs + + "#phy-cells": + const: 0 + + clocks: + items: + - description: PCIe PHY reference clock + + num-lanes: + const: 2 + + lcpll-ref-clk: + const: 1 + +required: + - compatible + - reg + - reg-names + - "#phy-cells" + - clocks + - clock-names + - samsung,fsys-sysreg + - num-lanes + - lcpll-ref-clk + +additionalProperties: true + +examples: + - | + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + pcie_phy: pcie-phy@16c80000 { + compatible = "axis,artpec8-pcie-phy"; + reg = <0x0 0x16c80000 0x0 0x2000>, + <0x0 0x16c90000 0x0 0x1000>; + reg-names = "phy", "pcs"; + #phy-cells = <0>; + clocks = <&clock_cmu_fsys 53>; + clock-names = "ref"; + samsung,fsys-sysreg = <&syscon_fsys>; + num-lanes = <2>; + lcpll-ref-clk = <1>; + }; + }; +... -- 2.9.5