From: Alexandru Gagniuc <mr.nuke.me@gmail.com>
To: "Bjorn Andersson" <andersson@kernel.org>,
"Konrad Dybcio" <konrad.dybcio@linaro.org>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Rob Herring" <robh@kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Vinod Koul" <vkoul@kernel.org>,
"Kishon Vijay Abraham I" <kishon@kernel.org>,
"Michael Turquette" <mturquette@baylibre.com>,
"Stephen Boyd" <sboyd@kernel.org>,
"Manivannan Sadhasivam" <manivannan.sadhasivam@linaro.org>,
linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-phy@lists.infradead.org, linux-clk@vger.kernel.org
Cc: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Subject: [PATCH v3 7/7] arm64: dts: qcom: ipq9574: add PCIe2 nodes
Date: Mon, 15 Apr 2024 13:20:52 -0500 [thread overview]
Message-ID: <20240415182052.374494-8-mr.nuke.me@gmail.com> (raw)
In-Reply-To: <20240415182052.374494-1-mr.nuke.me@gmail.com>
On ipq9574, there are 4 PCIe controllers. Describe the pcie2 node, and
its PHY in devicetree.
Only pcie2 is described, because only hardware using that controller
was available for testing.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
---
arch/arm64/boot/dts/qcom/ipq9574.dtsi | 93 ++++++++++++++++++++++++++-
1 file changed, 92 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
index 7f2e5cbf3bbb..f075e2715300 100644
--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
@@ -300,7 +300,7 @@ gcc: clock-controller@1800000 {
<0>,
<0>,
<0>,
- <0>,
+ <&pcie2_phy>,
<0>,
<0>;
#clock-cells = <1>;
@@ -745,6 +745,97 @@ frame@b128000 {
status = "disabled";
};
};
+
+ pcie2_phy: phy@8c000 {
+ compatible = "qcom,ipq9574-qmp-gen3x2-pcie-phy";
+ reg = <0x0008c000 0x14f4>;
+
+ clocks = <&gcc GCC_PCIE2_AUX_CLK>,
+ <&gcc GCC_PCIE2_AHB_CLK>,
+ <&gcc GCC_PCIE2_PIPE_CLK>,
+ <&gcc GCC_ANOC_PCIE2_2LANE_M_CLK>,
+ <&gcc GCC_SNOC_PCIE2_2LANE_S_CLK>;
+ clock-names = "aux",
+ "cfg_ahb",
+ "pipe",
+ "anoc",
+ "snoc";
+
+ clock-output-names = "pcie_phy2_pipe_clk";
+ #clock-cells = <0>;
+ #phy-cells = <0>;
+
+ resets = <&gcc GCC_PCIE2_PHY_BCR>,
+ <&gcc GCC_PCIE2PHY_PHY_BCR>;
+ reset-names = "phy",
+ "common";
+ status = "disabled";
+ };
+
+ pcie2: pcie@20000000 {
+ compatible = "qcom,pcie-ipq9574";
+ reg = <0x20000000 0xf1d>,
+ <0x20000f20 0xa8>,
+ <0x20001000 0x1000>,
+ <0x00088000 0x4000>,
+ <0x20100000 0x1000>;
+ reg-names = "dbi", "elbi", "atu", "parf", "config";
+
+ ranges = <0x81000000 0x0 0x20200000 0x20200000 0x0 0x00100000>, /* I/O */
+ <0x82000000 0x0 0x20300000 0x20300000 0x0 0x07d00000>; /* MEM */
+
+ device_type = "pci";
+ linux,pci-domain = <3>;
+ bus-range = <0x00 0xff>;
+ num-lanes = <2>;
+ max-link-speed = <3>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ phys = <&pcie2_phy>;
+ phy-names = "pciephy";
+
+ interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi";
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 0 164
+ IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+ <0 0 0 2 &intc 0 0 165
+ IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+ <0 0 0 3 &intc 0 0 186
+ IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+ <0 0 0 4 &intc 0 0 187
+ IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+ clocks = <&gcc GCC_PCIE2_AXI_M_CLK>,
+ <&gcc GCC_PCIE2_AXI_S_CLK>,
+ <&gcc GCC_PCIE2_AXI_S_BRIDGE_CLK>,
+ <&gcc GCC_PCIE2_RCHNG_CLK>;
+ clock-names = "axi_m",
+ "axi_s",
+ "axi_bridge",
+ "rchng";
+
+ resets = <&gcc GCC_PCIE2_PIPE_ARES>,
+ <&gcc GCC_PCIE2_AUX_ARES>,
+ <&gcc GCC_PCIE2_CORE_STICKY_ARES>,
+ <&gcc GCC_PCIE2_AXI_M_ARES>,
+ <&gcc GCC_PCIE2_AXI_S_ARES>,
+ <&gcc GCC_PCIE2_AXI_S_STICKY_ARES>,
+ <&gcc GCC_PCIE2_AXI_M_STICKY_ARES>,
+ <&gcc GCC_PCIE2_AHB_ARES>;
+ reset-names = "pipe",
+ "aux",
+ "sticky",
+ "axi_m",
+ "axi_s",
+ "axi_s_sticky",
+ "axi_m_sticky",
+ "ahb";
+ status = "disabled";
+ };
};
thermal-zones {
--
2.40.1
next prev parent reply other threads:[~2024-04-15 18:21 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-15 18:20 [PATCH v3 0/7] ipq9574: Enable PCI-Express support Alexandru Gagniuc
2024-04-15 18:20 ` [PATCH v3 1/7] dt-bindings: clock: Add PCIe pipe related clocks for IPQ9574 Alexandru Gagniuc
2024-04-15 18:20 ` [PATCH v3 2/7] clk: qcom: gcc-ipq9574: Add PCIe pipe clocks Alexandru Gagniuc
2024-04-15 20:04 ` Dmitry Baryshkov
2024-04-19 22:22 ` Stephen Boyd
2024-04-15 18:20 ` [PATCH v3 3/7] dt-bindings: PCI: qcom: Add IPQ9574 PCIe controller Alexandru Gagniuc
2024-04-18 12:59 ` Rob Herring
2024-04-15 18:20 ` [PATCH v3 4/7] PCI: qcom: Add support for IPQ9574 Alexandru Gagniuc
2024-04-15 20:04 ` Dmitry Baryshkov
2024-04-15 20:07 ` mr.nuke.me
2024-04-17 7:06 ` Manivannan Sadhasivam
2024-04-19 19:44 ` mr.nuke.me
2024-04-22 7:11 ` Manivannan Sadhasivam
2024-04-17 7:14 ` Manivannan Sadhasivam
2024-04-15 18:20 ` [PATCH v3 5/7] dt-bindings: phy: qcom,ipq8074-qmp-pcie: add ipq9574 gen3x2 PHY Alexandru Gagniuc
2024-04-18 13:00 ` Rob Herring
2024-04-15 18:20 ` [PATCH v3 6/7] phy: qcom-qmp-pcie: add support for " Alexandru Gagniuc
2024-04-15 20:10 ` Dmitry Baryshkov
2024-04-15 21:25 ` mr.nuke.me
2024-04-16 21:25 ` Alex G.
2024-04-16 21:50 ` Dmitry Baryshkov
2024-04-29 6:20 ` Varadarajan Narayanan
2024-04-29 10:55 ` Dmitry Baryshkov
2024-04-30 6:31 ` Varadarajan Narayanan
2024-04-30 21:51 ` mr.nuke.me
2024-04-30 21:59 ` Dmitry Baryshkov
2024-04-15 18:20 ` Alexandru Gagniuc [this message]
2024-04-17 7:34 ` [PATCH v3 7/7] arm64: dts: qcom: ipq9574: add PCIe2 nodes Manivannan Sadhasivam
2024-04-18 15:33 ` mr.nuke.me
2024-04-22 7:10 ` Manivannan Sadhasivam
2024-04-22 14:29 ` Konrad Dybcio
2024-04-19 14:28 ` [PATCH v3 0/7] ipq9574: Enable PCI-Express support Kathiravan Thirumoorthy
2024-04-19 19:47 ` mr.nuke.me
2024-04-23 6:11 ` Kathiravan Thirumoorthy
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20240415182052.374494-8-mr.nuke.me@gmail.com \
--to=mr.nuke.me@gmail.com \
--cc=andersson@kernel.org \
--cc=bhelgaas@google.com \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=kishon@kernel.org \
--cc=konrad.dybcio@linaro.org \
--cc=krzk+dt@kernel.org \
--cc=kw@linux.com \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-clk@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=linux-phy@lists.infradead.org \
--cc=lpieralisi@kernel.org \
--cc=manivannan.sadhasivam@linaro.org \
--cc=mturquette@baylibre.com \
--cc=robh@kernel.org \
--cc=sboyd@kernel.org \
--cc=vkoul@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).