From: Bjorn Helgaas <helgaas@kernel.org>
To: Heiner Kallweit <hkallweit1@gmail.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>,
"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>
Subject: Re: [PATCH v2] PCI: Annotate pci_cache_line_size variables as __ro_after_init
Date: Thu, 18 Apr 2024 13:46:44 -0500 [thread overview]
Message-ID: <20240418184644.GA246566@bhelgaas> (raw)
In-Reply-To: <52fd058d-6d72-48db-8e61-5fcddcd0aa51@gmail.com>
On Thu, Apr 18, 2024 at 08:29:21PM +0200, Heiner Kallweit wrote:
> Annotate both variables as __ro_after_init, enforcing that they can't
> be changed after the init phase.
>
> Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Applied to pci/misc for v6.10, thanks!
> ---
> v2:
> - remove annotation from extern declaration in pci.h
> ---
> drivers/pci/pci.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
> index 5f8edba78..59aaebb67 100644
> --- a/drivers/pci/pci.c
> +++ b/drivers/pci/pci.c
> @@ -142,8 +142,8 @@ enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_DEFAULT;
> * the dfl or actual value as it sees fit. Don't forget this is
> * measured in 32-bit words, not bytes.
> */
> -u8 pci_dfl_cache_line_size = L1_CACHE_BYTES >> 2;
> -u8 pci_cache_line_size;
> +u8 pci_dfl_cache_line_size __ro_after_init = L1_CACHE_BYTES >> 2;
> +u8 pci_cache_line_size __ro_after_init ;
>
> /*
> * If we set up a device for bus mastering, we need to check the latency
> --
> 2.44.0
prev parent reply other threads:[~2024-04-18 18:46 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-18 18:29 [PATCH v2] PCI: Annotate pci_cache_line_size variables as __ro_after_init Heiner Kallweit
2024-04-18 18:46 ` Bjorn Helgaas [this message]
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