From: David Laight <David.Laight@ACULAB.COM>
To: 'Bjorn Helgaas' <helgaas@kernel.org>,
Muni Sekhar <munisekharrms@gmail.com>
Cc: "linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: RE: pcie: xilinx: kernel hang - ISR readl()
Date: Fri, 31 Jan 2020 11:33:03 +0000 [thread overview]
Message-ID: <446f8f85815b480cb1e8cf477b74b1af@AcuMS.aculab.com> (raw)
In-Reply-To: <20200130190040.GA96992@google.com>
From: Bjorn Helgaas
> Sent: 30 January 2020 19:01
..
> > > You could learn this either via a PCIe analyzer (expensive piece of
> > > hardware) or possibly some logic in the FPGA that would log PCIe
> > > transactions in a buffer and make them accessible via some other
> > > interface (you mentioned it had parallel and other interfaces).
You can probably use the Xilinx equivalent of Altera 'signaltap'
to work out what is happening within the fpga.
David
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Registered Address Lakeside, Bramley Road, Mount Farm, Milton Keynes, MK1 1PT, UK
Registration No: 1397386 (Wales)
next prev parent reply other threads:[~2020-01-31 11:33 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-01-07 16:15 pcie: xilinx: kernel hang - ISR readl() Muni Sekhar
2020-01-08 14:33 ` Muni Sekhar
2020-01-08 20:15 ` Bjorn Helgaas
2020-01-09 3:17 ` Muni Sekhar
2020-01-09 4:35 ` Bjorn Helgaas
2020-01-09 4:50 ` Muni Sekhar
2020-01-18 1:46 ` Muni Sekhar
2020-01-28 17:40 ` Bjorn Helgaas
2020-01-30 16:07 ` Muni Sekhar
2020-01-30 19:00 ` Bjorn Helgaas
2020-01-31 11:33 ` David Laight [this message]
2020-01-31 16:34 ` Muni Sekhar
2020-01-31 20:46 ` Bjorn Helgaas
2020-02-01 3:14 ` Muni Sekhar
2020-02-01 18:29 ` Bjorn Helgaas
2020-02-04 15:33 ` Muni Sekhar
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