From: Dilip Kota <eswara.kota@linux.intel.com>
To: gustavo.pimentel@synopsys.com, lorenzo.pieralisi@arm.com,
andrew.murray@arm.com, helgaas@kernel.org, jingoohan1@gmail.com,
robh@kernel.org, martin.blumenstingl@googlemail.com,
linux-pci@vger.kernel.org, devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org, andriy.shevchenko@intel.com,
cheol.yong.kim@intel.com, chuanhua.lei@linux.intel.com,
qi-ming.wu@intel.com, Dilip Kota <eswara.kota@linux.intel.com>
Subject: [PATCH v5 1/3] dt-bindings: PCI: intel: Add YAML schemas for the PCIe RC controller
Date: Wed, 6 Nov 2019 11:44:01 +0800 [thread overview]
Message-ID: <73655e49e80ac08826ad2d470e1387ba1b662d83.1572950559.git.eswara.kota@linux.intel.com> (raw)
In-Reply-To: <cover.1572950559.git.eswara.kota@linux.intel.com>
In-Reply-To: <cover.1572950559.git.eswara.kota@linux.intel.com>
Add YAML schemas for PCIe RC controller on Intel Gateway SoCs
which is Synopsys DesignWare based PCIe core.
Signed-off-by: Dilip Kota <eswara.kota@linux.intel.com>
Reviewed-by: Andrew Murray <andrew.murray@arm.com>
---
Changes on v5:
Add Reviewed-by Andrew Murray.
Add possible values and default value for max-link-speed.
Remove $ref and add maximum and default for reset-assert-ms.
Set true flag for linux,pci-domain.
Define maxItems for ranges and clock.
Define maximum for num-lanes.
Update required list:
Add #address-cells, #size-cells, #interrupt-cells.
Remove num-lanes and linux,pci-domain.
Add required header files in example.
Remove status entry in example.
changes on v4:
Add "snps,dw-pcie" compatible.
Rename phy-names property value to pcie.
And maximum and minimum values to num-lanes.
Add ref for reset-assert-ms entry and update the
description for easy understanding.
Remove PCIe core interrupt entry.
changes on v3:
Add the appropriate License-Identifier
Rename intel,rst-interval to 'reset-assert-us'
Add additionalProperties: false
Rename phy-names to 'pciephy'
Remove the dtsi node split of SoC and board in the example
Add #interrupt-cells = <1>; or else interrupt parsing will fail
Name yaml file with compatible name
.../devicetree/bindings/pci/intel-gw-pcie.yaml | 138 +++++++++++++++++++++
1 file changed, 138 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml
diff --git a/Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml b/Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml
new file mode 100644
index 000000000000..db605d8a387d
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml
@@ -0,0 +1,138 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/intel-gw-pcie.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: PCIe RC controller on Intel Gateway SoCs
+
+maintainers:
+ - Dilip Kota <eswara.kota@linux.intel.com>
+
+properties:
+ compatible:
+ items:
+ - const: intel,lgm-pcie
+ - const: snps,dw-pcie
+
+ device_type:
+ const: pci
+
+ "#address-cells":
+ const: 3
+
+ "#size-cells":
+ const: 2
+
+ reg:
+ items:
+ - description: Controller control and status registers.
+ - description: PCIe configuration registers.
+ - description: Controller application registers.
+
+ reg-names:
+ items:
+ - const: dbi
+ - const: config
+ - const: app
+
+ ranges:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ phys:
+ maxItems: 1
+
+ phy-names:
+ const: pcie
+
+ reset-gpios:
+ maxItems: 1
+
+ linux,pci-domain: true
+
+ num-lanes:
+ maximum: 2
+ description: Number of lanes to use for this port.
+
+ '#interrupt-cells':
+ const: 1
+
+ interrupt-map-mask:
+ description: Standard PCI IRQ mapping properties.
+
+ interrupt-map:
+ description: Standard PCI IRQ mapping properties.
+
+ max-link-speed:
+ description: Specify PCI Gen for link capability.
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32
+ - enum: [ 1, 2, 3, 4 ]
+ - default: 1
+
+ bus-range:
+ description: Range of bus numbers associated with this controller.
+
+ reset-assert-ms:
+ description: |
+ Delay after asserting reset to the PCIe device.
+ maximum: 500
+ default: 100
+
+required:
+ - compatible
+ - device_type
+ - "#address-cells"
+ - "#size-cells"
+ - reg
+ - reg-names
+ - ranges
+ - resets
+ - clocks
+ - phys
+ - phy-names
+ - reset-gpios
+ - '#interrupt-cells'
+ - interrupt-map
+ - interrupt-map-mask
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/clock/intel,lgm-clk.h>
+ pcie10: pcie@d0e00000 {
+ compatible = "intel,lgm-pcie", "snps,dw-pcie";
+ device_type = "pci";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ reg = <0xd0e00000 0x1000>,
+ <0xd2000000 0x800000>,
+ <0xd0a41000 0x1000>;
+ reg-names = "dbi", "config", "app";
+ linux,pci-domain = <0>;
+ max-link-speed = <4>;
+ bus-range = <0x00 0x08>;
+ interrupt-parent = <&ioapic1>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &ioapic1 27 1>,
+ <0 0 0 2 &ioapic1 28 1>,
+ <0 0 0 3 &ioapic1 29 1>,
+ <0 0 0 4 &ioapic1 30 1>;
+ ranges = <0x02000000 0 0xd4000000 0xd4000000 0 0x04000000>;
+ resets = <&rcu0 0x50 0>;
+ clocks = <&cgu0 LGM_GCLK_PCIE10>;
+ phys = <&cb0phy0>;
+ phy-names = "pcie";
+ reset-assert-ms = <500>;
+ reset-gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
+ num-lanes = <2>;
+ };
--
2.11.0
next prev parent reply other threads:[~2019-11-06 3:44 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-06 3:44 [PATCH v5 0/3] PCI: Add Intel PCIe Driver and respective dt-binding yaml file Dilip Kota
2019-11-06 3:44 ` Dilip Kota [this message]
2019-11-12 19:17 ` [PATCH v5 1/3] dt-bindings: PCI: intel: Add YAML schemas for the PCIe RC controller Rob Herring
2019-11-13 2:39 ` Dilip Kota
2019-11-06 3:44 ` [PATCH v5 2/3] dwc: PCI: intel: PCIe RC controller driver Dilip Kota
2019-11-06 12:24 ` Andy Shevchenko
2019-11-11 8:08 ` Dilip Kota
2019-11-12 7:18 ` Dilip Kota
2019-11-08 10:42 ` Andrew Murray
2019-11-11 8:09 ` Dilip Kota
2019-11-06 3:44 ` [PATCH v5 3/3] PCI: artpec6: Configure FTS with dwc helper function Dilip Kota
2019-11-06 9:43 ` Gustavo Pimentel
2019-11-11 6:24 ` Dilip Kota
2019-11-07 21:03 ` Jingoo Han
2019-11-08 10:43 ` Andrew Murray
2019-11-11 8:10 ` Dilip Kota
2019-11-11 8:09 ` Dilip Kota
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=73655e49e80ac08826ad2d470e1387ba1b662d83.1572950559.git.eswara.kota@linux.intel.com \
--to=eswara.kota@linux.intel.com \
--cc=andrew.murray@arm.com \
--cc=andriy.shevchenko@intel.com \
--cc=cheol.yong.kim@intel.com \
--cc=chuanhua.lei@linux.intel.com \
--cc=devicetree@vger.kernel.org \
--cc=gustavo.pimentel@synopsys.com \
--cc=helgaas@kernel.org \
--cc=jingoohan1@gmail.com \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=lorenzo.pieralisi@arm.com \
--cc=martin.blumenstingl@googlemail.com \
--cc=qi-ming.wu@intel.com \
--cc=robh@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).