From: <Austin.Bolen@dell.com>
To: <sathyanarayanan.kuppuswamy@linux.intel.com>,
<helgaas@kernel.org>, <Austin.Bolen@dell.com>
Cc: <linux-pci@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<ashok.raj@intel.com>
Subject: Re: [PATCH v17 09/12] PCI/AER: Allow clearing Error Status Register in FF mode
Date: Wed, 11 Mar 2020 21:53:30 +0000 [thread overview]
Message-ID: <868a9cc8b34f428e8f59c1b0213131d7@AUSX13MPC107.AMER.DELL.COM> (raw)
In-Reply-To: ddf5d142-09e7-67ee-16e4-37447df6b112@linux.intel.com
On 3/11/2020 4:27 PM, Kuppuswamy Sathyanarayanan wrote:
>
> [EXTERNAL EMAIL]
>
> Hi,
>
> On 3/11/20 1:33 PM, Bjorn Helgaas wrote:
>> On Wed, Mar 11, 2020 at 05:27:35PM +0000, Austin.Bolen@dell.com wrote:
>>> On 3/11/2020 12:12 PM, Bjorn Helgaas wrote:
>>>> [EXTERNAL EMAIL]
>>>>
>>> <SNIP>
>>>> I'm probably missing your intent, but that sounds like "the OS can
>>>> read/write AER bits whenever it wants, regardless of ownership."
>>>>
>>>> That doesn't sound practical to me, and I don't think it's really
>>>> similar to DPC, where it's pretty clear that the OS can touch DPC bits
>>>> it doesn't own but only *during the EDR processing window*.
>>> Yes, by treating AER bits like DPC bits I meant I'd define the specific
>>> time windows when OS can touch the AER status bits similar to how it's
>>> done for DPC in the current ECN.
>> Makes sense, thanks.
>>
>>>>>>> For the normative text describing when OS clears the AER bits
>>>>>>> following the informative flow chart, it could say that OS clears
>>>>>>> AER as soon as possible after OST returns and before OS processes
>>>>>>> _HPX and loading drivers. Open to other suggestions as well.
>>>>>> I'm not sure what to do with "as soon as possible" either. That
>>>>>> doesn't seem like something firmware and the OS can agree on.
>>>>> I can just state that it's done after OST returns but before _HPX or
>>>>> driver is loaded. Any time in that range is fine. I can't get super
>>>>> specific here because different OSes do different things. Even for
>>>>> a given OS they change over time. And I need something generic
>>>>> enough to support a wide variety of OS implementations.
>>>> Yeah. I don't know how to solve this.
>>>>
>>>> Linux doesn't actually unload and reload drivers for the child devices
>>>> (Sathy, correct me if I'm wrong here) even though DPC containment
>>>> takes the link down and effectively unplugs and replugs the device. I
>>>> would *like* to handle it like hotplug, but some higher-level software
>>>> doesn't deal well with things like storage devices disappearing and
>>>> reappearing.
>>>>
>>>> Since Linux doesn't actually re-enumerate the child devices, it
>>>> wouldn't evaluate _HPX again. It would probably be cleaner if it did,
>>>> but it's all tied up with the whole unplug/replug problem.
>>> DPC resets everything below it and so to get it back up and running it
>>> would mean that all buses and resources need to be assigned, _HPX
>>> evaluated, and drivers reloaded. If those things don't happen then the
>>> whole hierarchy below the port that triggered DPC will be inaccessible.
>> Hmm, I think I might be confusing this with another situation. Sathy,
>> can you help me understand this? I don't have a way to actually
>> exercise this EDR path. Is there some way the pciehp hotplug driver
>> gets involved here?
If the port has hot-plug enabled then DPC trigger will cause the link to
go down (disabled state) and will generate a DLLSC hot-plug interrupt.
When DPC is released, the link will become active and generate another
DLLSC hot-plug interrupt.
>>
>> Here's how this seems to work as far as I can tell:
>>
>> - Linux does not have DPC or AER control
>>
>> - Linux installs EDR notify handler
>>
>> - Linux evaluates DPC Enable _DSM
>>
>> - DPC containment event occurs
>>
>> - Firmware fields DPC interrupt
>>
>> - DPC event is not a surprise remove
>>
>> - Firmware sends EDR notification
>>
>> - Linux EDR notify handler evaluates Locate _DSM
>>
>> - Linux reads and logs DPC and AER error information for port in
>> containment mode. [If it was an RP PIO error, Linux clears RP PIO
>> error status, which is an asymmetry with the non-RP PIO path.]
>>
>> - Linux clears AER error status (pci_aer_raw_clear_status())
>>
>> - Linux calls driver .error_detected() methods for all child devices
>> of the port in containment mode (pcie_do_recovery()). These
>> devices are inaccessible because the link is down.
>>
>> - Linux clears DPC Trigger Status (dpc_reset_link() from
>> pcie_do_recovery()).
>>
>> - Linux calls driver .mmio_enabled() methods for all child devices.
>>
>> This is where I get lost. These child devices are now accessible, but
>> they've been reset, so I don't know how their config space got
>> restored. Did pciehp enumerate them? Did we do something like
>> pci_restore_state()? I don't see where either of these happens.
> AFAIK, AER error status registers are sticky (RW1CS) and hence
> will be preserved during reset.
In our testing, the device directly connected to the port that was
contained does get reprogrammed and the driver is reloaded. These are
hot-plug slots and so might be due to DLLSC hot-plug interrupt when
containment is released and link goes back to active state.
However, if a switch is connected to the port where DPC was triggered
then we do not see the whole switch hierarchy being re-enumerated.
Also, DPC could be enabled on non-hot-plug slots so can't always rely on
hot-plug to re-init devices in the recovery path.
>>
>> So they want to basically do native AER handling even though firmware
>> owns AER? My head hurts.
> No, Its meant only for clearing AER registers. In EDR path, since
> OS owns clearing DPC registers, they want to let OS own clearing AER
> registers as well. Also, it would give OS a chance to decide whether
> we want to keep the device on based on error status and history of the
> device attached.
Right. The way it was pitched to me was that the OSVs wanted to
read/clear the error status bits so they could re-use the code that does
that when OS natively owns AER/DPC.
>>
>> Bjorn
>
next prev parent reply other threads:[~2020-03-11 21:53 UTC|newest]
Thread overview: 67+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-04 2:36 [PATCH v17 00/12] Add Error Disconnect Recover (EDR) support sathyanarayanan.kuppuswamy
2020-03-04 2:36 ` [PATCH v17 01/12] PCI/ERR: Update error status after reset_link() sathyanarayanan.kuppuswamy
2020-03-04 2:36 ` [PATCH v17 02/12] PCI/AER: Move pci_cleanup_aer_error_status_regs() declaration to pci.h sathyanarayanan.kuppuswamy
2020-03-04 2:36 ` [PATCH v17 03/12] PCI/ERR: Remove service dependency in pcie_do_recovery() sathyanarayanan.kuppuswamy
2020-03-17 14:40 ` Christoph Hellwig
2020-03-04 2:36 ` [PATCH v17 04/12] PCI: portdrv: remove unnecessary pcie_port_find_service() sathyanarayanan.kuppuswamy
2020-03-04 2:36 ` [PATCH v17 05/12] PCI: portdrv: remove reset_link member from pcie_port_service_driver sathyanarayanan.kuppuswamy
2020-03-17 14:41 ` Christoph Hellwig
2020-03-17 14:55 ` Kuppuswamy, Sathyanarayanan
2020-03-04 2:36 ` [PATCH v17 06/12] Documentation: PCI: Remove reset_link references sathyanarayanan.kuppuswamy
2020-03-17 14:42 ` Christoph Hellwig
2020-03-17 15:05 ` Kuppuswamy, Sathyanarayanan
2020-03-17 15:07 ` Christoph Hellwig
2020-03-17 16:03 ` Bjorn Helgaas
2020-03-17 17:06 ` Christoph Hellwig
2020-03-19 22:52 ` Bjorn Helgaas
2020-03-04 2:36 ` [PATCH v17 07/12] PCI/ERR: Return status of pcie_do_recovery() sathyanarayanan.kuppuswamy
2020-03-04 2:36 ` [PATCH v17 08/12] PCI/DPC: Cache DPC capabilities in pci_init_capabilities() sathyanarayanan.kuppuswamy
2020-03-04 2:36 ` [PATCH v17 09/12] PCI/AER: Allow clearing Error Status Register in FF mode sathyanarayanan.kuppuswamy
2020-03-06 5:45 ` Kuppuswamy, Sathyanarayanan
2020-03-06 16:04 ` Bjorn Helgaas
2020-03-06 16:11 ` Kuppuswamy, Sathyanarayanan
2020-03-06 16:41 ` Bjorn Helgaas
2020-03-10 2:40 ` Bjorn Helgaas
2020-03-10 4:28 ` Kuppuswamy, Sathyanarayanan
2020-03-10 18:14 ` Austin.Bolen
2020-03-10 19:32 ` Bjorn Helgaas
2020-03-10 20:06 ` Austin.Bolen
2020-03-10 20:41 ` Kuppuswamy Sathyanarayanan
2020-03-10 20:49 ` Austin.Bolen
2020-03-11 14:45 ` Bjorn Helgaas
2020-03-11 15:19 ` Austin.Bolen
2020-03-11 17:12 ` Bjorn Helgaas
2020-03-11 17:27 ` Austin.Bolen
2020-03-11 20:33 ` Bjorn Helgaas
2020-03-11 21:25 ` Kuppuswamy Sathyanarayanan
2020-03-11 21:53 ` Austin.Bolen [this message]
2020-03-11 22:11 ` Kuppuswamy Sathyanarayanan
2020-03-11 22:23 ` Bjorn Helgaas
2020-03-11 23:07 ` Kuppuswamy Sathyanarayanan
2020-03-12 19:53 ` Bjorn Helgaas
2020-03-12 21:02 ` Austin.Bolen
2020-03-12 21:29 ` Kuppuswamy Sathyanarayanan
2020-03-12 21:52 ` Bjorn Helgaas
2020-03-12 22:02 ` Kuppuswamy Sathyanarayanan
2020-03-12 22:36 ` Bjorn Helgaas
2020-03-12 21:59 ` Kuppuswamy Sathyanarayanan
2020-03-12 22:32 ` Bjorn Helgaas
2020-03-13 6:22 ` Kuppuswamy, Sathyanarayanan
2020-03-13 19:28 ` Bjorn Helgaas
2020-03-13 20:26 ` Kuppuswamy Sathyanarayanan
2020-03-19 23:03 ` Bjorn Helgaas
2020-03-19 23:20 ` Kuppuswamy, Sathyanarayanan
2020-03-11 22:13 ` Bjorn Helgaas
2020-03-11 22:41 ` Kuppuswamy Sathyanarayanan
2020-03-11 18:12 ` Kuppuswamy Sathyanarayanan
2020-03-11 22:05 ` Bjorn Helgaas
2020-03-04 2:36 ` [PATCH v17 10/12] PCI/DPC: Export DPC error recovery functions sathyanarayanan.kuppuswamy
2020-03-17 14:43 ` Christoph Hellwig
2020-03-04 2:36 ` [PATCH v17 11/12] PCI/DPC: Add Error Disconnect Recover (EDR) support sathyanarayanan.kuppuswamy
2020-03-06 3:47 ` Bjorn Helgaas
2020-03-06 6:32 ` Kuppuswamy, Sathyanarayanan
2020-03-06 21:00 ` Bjorn Helgaas
2020-03-06 22:42 ` Kuppuswamy Sathyanarayanan
2020-03-06 23:23 ` Bjorn Helgaas
2020-03-07 0:19 ` Kuppuswamy Sathyanarayanan
2020-03-04 2:36 ` [PATCH v17 12/12] PCI/ACPI: Enable EDR support sathyanarayanan.kuppuswamy
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