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From: Thomas Gleixner <tglx@linutronix.de>
To: Bjorn Helgaas <helgaas@kernel.org>, Dave Jiang <dave.jiang@intel.com>
Cc: vkoul@kernel.org, mingo@redhat.com, bp@alien8.de, hpa@zytor.com,
	gregkh@linuxfoundation.org, arnd@arndb.de,
	linux-kernel@vger.kernel.org, x86@kernel.org,
	dmaengine@vger.kernel.org, dan.j.williams@intel.com,
	ashok.raj@intel.com, fenghua.yu@intel.com,
	linux-pci@vger.kernel.org, tony.luck@intel.com,
	jing.lin@intel.com, sanjay.k.kumar@intel.com
Subject: Re: [PATCH 2/6] device/pci: add cmdmem cap to pci_dev
Date: Wed, 01 Apr 2020 00:34:06 +0200	[thread overview]
Message-ID: <87ftdoupb5.fsf@nanos.tec.linutronix.de> (raw)
In-Reply-To: <20200331220006.GA37376@google.com>

Bjorn Helgaas <helgaas@kernel.org> writes:
> On Tue, Mar 31, 2020 at 10:59:44AM -0700, Dave Jiang wrote:
>> On 3/31/2020 9:03 AM, Bjorn Helgaas wrote:
>> > On Mon, Mar 30, 2020 at 02:27:00PM -0700, Dave Jiang wrote:
>> > > Since the current accelerator devices do not have standard PCIe capability
>> > > enumeration for accepting ENQCMDS yet, for now an attribute of pdev->cmdmem has
>> > > been added to struct pci_dev.  Currently a PCI quirk must be used for the
>> > > devices that have such cap until the PCI cap is standardized. Add a helper
>> > > function to provide the check if a device supports the cmdmem capability.
>> > > 
>> > > Such capability is expected to be added to PCIe device cap enumeration in
>> > > the future.
>> > This needs some sort of thumbnail description of what "synchronous
>> > write notification" and "cmdmem" mean.
>> 
>> I will add more explanation.
>> 
>> > Do you have a pointer to a PCI-SIG ECR or similar?
>> 
>> Deferrable Memory Write (DMWr) ECR
>> 
>> https://members.pcisig.com/wg/PCI-SIG/document/13747
>> 
>> From what I'm told it should be available for public review by EOW.
>
> Please use terminology from the spec instead of things like
> "synchronous write notification".
>
> AIUI, ENQCMDS is an x86 instruction.  That would have no meaning in
> the PCIe domain.
>
> I'm not committing to acking any part of this before the ECR is
> accepted, but if you're adding support for the feature described by
> the ECR, you might as well add support for discovering the DMWr
> capability via Device Capabilities 2 as described in the ECR.

Don't worry. There is nothing to decide and ack before the basic
architecture support for ENQCMD[S] is discussed and accepted. The
patches providing this support have been posted 2 hrs before this pile
hit the mailing lists yesterday.

Thanks,

        tglx


  reply	other threads:[~2020-03-31 22:34 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <d798a7eb-ceb0-d81e-5422-f9e41058a098@intel.com>
2020-03-31 22:00 ` [PATCH 2/6] device/pci: add cmdmem cap to pci_dev Bjorn Helgaas
2020-03-31 22:34   ` Thomas Gleixner [this message]
2020-04-01 16:37   ` Dave Jiang
2020-03-30 21:26 [PATCH 0/6] Add shared workqueue support for idxd driver Dave Jiang
2020-03-30 21:27 ` [PATCH 2/6] device/pci: add cmdmem cap to pci_dev Dave Jiang
2020-03-31 10:04   ` Greg KH
2020-03-31 17:07     ` Dave Jiang
2020-03-31 17:24       ` Greg KH
2020-03-31 17:38         ` Dave Jiang
2020-03-31 16:03   ` Bjorn Helgaas
2020-03-31 21:44     ` Dave Jiang

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