From: "Z.q. Hou" <zhiqiang.hou@nxp.com>
To: "linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"bhelgaas@google.com" <bhelgaas@google.com>,
"robh+dt@kernel.org" <robh+dt@kernel.org>,
"mark.rutland@arm.com" <mark.rutland@arm.com>,
"l.subrahmanya@mobiveil.co.in" <l.subrahmanya@mobiveil.co.in>,
"shawnguo@kernel.org" <shawnguo@kernel.org>,
Leo Li <leoyang.li@nxp.com>,
"lorenzo.pieralisi@arm.com" <lorenzo.pieralisi@arm.com>,
"catalin.marinas@arm.com" <catalin.marinas@arm.com>,
"will.deacon@arm.com" <will.deacon@arm.com>
Cc: Mingkai Hu <mingkai.hu@nxp.com>,
"M.h. Lian" <minghuan.lian@nxp.com>,
Xiaowei Bao <xiaowei.bao@nxp.com>
Subject: RE: [PATCHv4 23/28] dt-bindings: pci: Add NXP Layerscape SoCs PCIe Gen4 controller
Date: Tue, 12 Mar 2019 09:42:36 +0000 [thread overview]
Message-ID: <AM6PR04MB57811882B16E9DA956A515E684490@AM6PR04MB5781.eurprd04.prod.outlook.com> (raw)
In-Reply-To: <20190311093130.7209-24-Zhiqiang.Hou@nxp.com>
Hi All,
Please ignore this, has re-sent it adding lost Reviewed-by tag.
Thanks,
Zhiqiang
> -----Original Message-----
> From: Z.q. Hou
> Sent: 2019年3月11日 17:33
> To: linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org;
> bhelgaas@google.com; robh+dt@kernel.org; mark.rutland@arm.com;
> l.subrahmanya@mobiveil.co.in; shawnguo@kernel.org; Leo Li
> <leoyang.li@nxp.com>; lorenzo.pieralisi@arm.com;
> catalin.marinas@arm.com; will.deacon@arm.com
> Cc: Mingkai Hu <mingkai.hu@nxp.com>; M.h. Lian
> <minghuan.lian@nxp.com>; Xiaowei Bao <xiaowei.bao@nxp.com>; Z.q. Hou
> <zhiqiang.hou@nxp.com>
> Subject: [PATCHv4 23/28] dt-bindings: pci: Add NXP Layerscape SoCs PCIe
> Gen4 controller
>
> From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
>
> Add PCIe Gen4 controller DT bindings of NXP Layerscape SoCs.
>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---
> V4:
> - no change
>
> .../bindings/pci/layerscape-pci-gen4.txt | 52 +++++++++++++++++++
> MAINTAINERS | 8 +++
> 2 files changed, 60 insertions(+)
> create mode 100644
> Documentation/devicetree/bindings/pci/layerscape-pci-gen4.txt
>
> diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci-gen4.txt
> b/Documentation/devicetree/bindings/pci/layerscape-pci-gen4.txt
> new file mode 100644
> index 000000000000..b40fb5d15d3d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/layerscape-pci-gen4.txt
> @@ -0,0 +1,52 @@
> +NXP Layerscape PCIe Gen4 controller
> +
> +This PCIe controller is based on the Mobiveil PCIe IP and thus inherits
> +all the common properties defined in mobiveil-pcie.txt.
> +
> +Required properties:
> +- compatible: should contain the platform identifier such as:
> + "fsl,lx2160a-pcie"
> +- reg: base addresses and lengths of the PCIe controller register blocks.
> + "csr_axi_slave": Bridge config registers
> + "config_axi_slave": PCIe controller registers
> +- interrupts: A list of interrupt outputs of the controller. Must
> +contain an
> + entry for each entry in the interrupt-names property.
> +- interrupt-names: It could include the following entries:
> + "intr": The interrupt that is asserted for controller interrupts
> + "aer": Asserted for aer interrupt when chip support the aer interrupt with
> + none MSI/MSI-X/INTx mode,but there is interrupt line for aer.
> + "pme": Asserted for pme interrupt when chip support the pme interrupt
> with
> + none MSI/MSI-X/INTx mode,but there is interrupt line for pme.
> +- dma-coherent: Indicates that the hardware IP block can ensure the
> +coherency
> + of the data transferred from/to the IP block. This can avoid the
> +software
> + cache flush/invalid actions, and improve the performance significantly.
> +- msi-parent : See the generic MSI binding described in
> + Documentation/devicetree/bindings/interrupt-controller/msi.txt.
> +
> +Example:
> +
> + pcie@3400000 {
> + compatible = "fsl,lx2160a-pcie";
> + reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers
> */
> + 0x80 0x00000000 0x0 0x00001000>; /* configuration space
> */
> + reg-names = "csr_axi_slave", "config_axi_slave";
> + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* AER
> interrupt */
> + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt
> */
> + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* controller
> interrupt */
> + interrupt-names = "aer", "pme", "intr";
> + #address-cells = <3>;
> + #size-cells = <2>;
> + device_type = "pci";
> + apio-wins = <8>;
> + ppio-wins = <8>;
> + dma-coherent;
> + bus-range = <0x0 0xff>;
> + msi-parent = <&its>;
> + ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0
> 0x40000000>;
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 7>;
> + interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109
> IRQ_TYPE_LEVEL_HIGH>,
> + <0000 0 0 2 &gic 0 0 GIC_SPI 110
> IRQ_TYPE_LEVEL_HIGH>,
> + <0000 0 0 3 &gic 0 0 GIC_SPI 111
> IRQ_TYPE_LEVEL_HIGH>,
> + <0000 0 0 4 &gic 0 0 GIC_SPI 112
> IRQ_TYPE_LEVEL_HIGH>;
> + };
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 1013e74b14f2..2d18c7213991 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -11835,6 +11835,14 @@ L: linux-arm-kernel@lists.infradead.org
> S: Maintained
> F: drivers/pci/controller/dwc/*layerscape*
>
> +PCI DRIVER FOR NXP LAYERSCAPE GEN4 CONTROLLER
> +M: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> +L: linux-pci@vger.kernel.org
> +L: linux-arm-kernel@lists.infradead.org
> +S: Maintained
> +F: Documentation/devicetree/bindings/pci/layerscape-pci-gen4.txt
> +F: drivers/pci/controller/mobibeil/pci-layerscape-gen4.c
> +
> PCI DRIVER FOR GENERIC OF HOSTS
> M: Will Deacon <will.deacon@arm.com>
> L: linux-pci@vger.kernel.org
> --
> 2.17.1
next prev parent reply other threads:[~2019-03-12 9:42 UTC|newest]
Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-11 9:29 [PATCHv4 00/28] PCI: refactor Mobiveil driver and add PCIe Gen4 driver for NXP Layerscape SoCs Z.q. Hou
2019-03-11 9:30 ` [PATCHv4 01/28] PCI: mobiveil: uniform the register accessors Z.q. Hou
2019-03-11 9:30 ` [PATCHv4 02/28] PCI: mobiveil: format the code without function change Z.q. Hou
2019-03-11 9:30 ` [PATCHv4 03/28] PCI: mobiveil: correct the returned error number Z.q. Hou
2019-03-11 9:30 ` [PATCHv4 04/28] PCI: mobiveil: remove flag MSI_FLAG_MULTI_PCI_MSI Z.q. Hou
2019-03-11 9:30 ` [PATCHv4 05/28] PCI: mobiveil: correct PCI base address in MEM/IO outbound windows Z.q. Hou
2019-03-11 9:30 ` [PATCHv4 06/28] PCI: mobiveil: replace the resource list iteration function Z.q. Hou
2019-03-11 9:30 ` [PATCHv4 07/28] PCI: mobiveil: use WIN_NUM_0 explicitly for CFG outbound window Z.q. Hou
2019-03-11 9:31 ` [PATCHv4 08/28] PCI: mobiveil: use the 1st inbound window for MEM inbound transactions Z.q. Hou
2019-03-11 9:31 ` [PATCHv4 09/28] PCI: mobiveil: correct inbound/outbound window setup routines Z.q. Hou
2019-03-11 9:31 ` [PATCHv4 10/28] PCI: mobiveil: fix the INTx process error Z.q. Hou
2019-03-11 14:08 ` Bjorn Helgaas
2019-03-12 4:42 ` Z.q. Hou
2019-03-11 9:31 ` [PATCHv4 11/28] PCI: mobiveil: only fix up the Class Code field Z.q. Hou
2019-03-11 14:14 ` Bjorn Helgaas
2019-03-12 9:17 ` Z.q. Hou
2019-03-13 10:59 ` Subrahmanya Lingappa
2019-03-11 9:31 ` [PATCHv4 12/28] PCI: mobiveil: move out the link up waiting from mobiveil_host_init Z.q. Hou
2019-03-11 9:31 ` [PATCHv4 13/28] PCI: mobiveil: move irq chained handler setup out of DT parse Z.q. Hou
2019-03-11 9:31 ` [PATCHv4 14/28] PCI: mobiveil: initialize Primary/Secondary/Subordinate bus number Z.q. Hou
2019-03-11 9:31 ` [PATCHv4 15/28] dt-bindings: pci: mobiveil: change gpio_slave and apb_csr to optional Z.q. Hou
2019-03-11 9:32 ` [PATCHv4 16/28] PCI: mobiveil: refactor Mobiveil PCIe Host Bridge IP driver Z.q. Hou
2019-03-26 17:34 ` Lorenzo Pieralisi
2019-03-27 2:04 ` Z.q. Hou
2019-03-27 17:39 ` Lorenzo Pieralisi
2019-03-28 2:09 ` Z.q. Hou
2019-03-28 16:09 ` Lorenzo Pieralisi
2019-03-29 6:07 ` Z.q. Hou
2019-03-11 9:32 ` [PATCHv4 17/28] PCI: mobiveil: fix the checking of valid device Z.q. Hou
2019-03-11 9:32 ` [PATCHv4 18/28] PCI: mobiveil: add link up condition check Z.q. Hou
2019-03-11 9:32 ` [PATCHv4 19/28] PCI: mobiveil: continue to initialize the host upon no PCIe link Z.q. Hou
2019-03-11 9:32 ` [PATCHv4 20/28] PCI: mobiveil: disabled IB and OB windows set by bootloader Z.q. Hou
2019-03-11 9:32 ` [PATCHv4 21/28] PCI: mobiveil: add Byte and Half-Word width register accessors Z.q. Hou
2019-03-11 9:32 ` [PATCHv4 22/28] PCI: mobiveil: make mobiveil_host_init can be used to re-init host Z.q. Hou
2019-03-11 9:33 ` [PATCHv4 23/28] dt-bindings: pci: Add NXP Layerscape SoCs PCIe Gen4 controller Z.q. Hou
2019-03-11 22:11 ` Rob Herring
2019-03-12 3:17 ` Z.q. Hou
2019-03-12 9:42 ` Z.q. Hou [this message]
2019-03-11 9:33 ` [PATCHv4 24/28] PCI: mobiveil: add PCIe Gen4 RC driver for NXP Layerscape SoCs Z.q. Hou
2019-03-11 14:01 ` Bjorn Helgaas
2019-03-12 4:40 ` Z.q. Hou
2019-03-11 9:33 ` [PATCHv4 25/28] PCI: mobiveil: ls_pcie_g4: add Workaround for A-011577 Z.q. Hou
2019-03-13 14:51 ` Z.q. Hou
2019-03-11 9:33 ` [PATCHv4 26/28] PCI: mobiveil: ls_pcie_g4: add Workaround for A-011451 Z.q. Hou
2019-03-11 17:34 ` Bjorn Helgaas
2019-03-12 9:34 ` Z.q. Hou
2019-03-12 13:34 ` Bjorn Helgaas
2019-03-13 14:49 ` Z.q. Hou
2019-03-13 14:51 ` Z.q. Hou
2019-03-11 9:33 ` [PATCHv4 27/28] arm64: dts: freescale: lx2160a: add pcie DT nodes Z.q. Hou
2019-03-11 9:33 ` [PATCHv4 28/28] arm64: defconfig: Enable CONFIG_PCI_LAYERSCAPE_GEN4 Z.q. Hou
2019-03-11 13:33 ` [PATCHv4 00/28] PCI: refactor Mobiveil driver and add PCIe Gen4 driver for NXP Layerscape SoCs Bjorn Helgaas
2019-03-12 4:18 ` Z.q. Hou
2019-03-26 17:37 ` Lorenzo Pieralisi
2019-03-27 2:11 ` Z.q. Hou
2019-03-12 9:38 [PATCHv4 23/28] dt-bindings: pci: Add NXP Layerscape SoCs PCIe Gen4 controller Z.q. Hou
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