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Tue, 23 Mar 2021 11:17:48 +0000 From: Bharat Kumar Gogada To: Bharat Kumar Gogada , "linux-pci@vger.kernel.org" , "linux-kernel@vger.kernel.org" CC: "bhelgaas@google.com" , "lorenzo.pieralisi@arm.com" Subject: RE: [PATCH v3 1/2] PCI: xilinx-nwl: Enable coherent PCIe DMA traffic using CCI Thread-Topic: [PATCH v3 1/2] PCI: xilinx-nwl: Enable coherent PCIe DMA traffic using CCI Thread-Index: AQHXCPdf8/XRKTi3FEaC06+ar6fH8aqEsnBAgAzn4TA= Date: Tue, 23 Mar 2021 11:17:48 +0000 Message-ID: References: <20210222084732.21521-1-bharat.kumar.gogada@xilinx.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-TNEF-Correlator: authentication-results: xilinx.com; dkim=none (message not signed) header.d=none;xilinx.com; dmarc=none action=none header.from=xilinx.com; x-originating-ip: [149.199.50.129] x-ms-publictraffictype: Email x-ms-office365-filtering-ht: Tenant x-ms-office365-filtering-correlation-id: 9b3154ec-6477-4e21-bd4d-08d8eded4a75 x-ms-traffictypediagnostic: BY5PR02MB6961: x-ld-processed: 657af505-d5df-48d0-8300-c31994686c5c,ExtAddr x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:3383; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BYAPR02MB5559.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 9b3154ec-6477-4e21-bd4d-08d8eded4a75 X-MS-Exchange-CrossTenant-originalarrivaltime: 23 Mar 2021 11:17:48.3158 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: KCWKl3X6fVt1iYWRBnzprBxDALmBFLPVhCZ1D3s4Sdr9LbdIDkrtlr729ULSrBYjCJgrHixlf4HAIjtunnYByQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR02MB6961 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Ping. > -----Original Message----- > From: Bharat Kumar Gogada > Sent: Monday, March 15, 2021 11:43 AM > To: Bharat Kumar Gogada ; linux- > pci@vger.kernel.org; linux-kernel@vger.kernel.org > Cc: bhelgaas@google.com > Subject: RE: [PATCH v3 1/2] PCI: xilinx-nwl: Enable coherent PCIe DMA tra= ffic > using CCI >=20 > Ping. >=20 > > -----Original Message----- > > From: Bharat Kumar Gogada > > Sent: Monday, February 22, 2021 2:18 PM > > To: linux-pci@vger.kernel.org; linux-kernel@vger.kernel.org > > Cc: bhelgaas@google.com; Bharat Kumar Gogada > > Subject: [PATCH v3 1/2] PCI: xilinx-nwl: Enable coherent PCIe DMA > > traffic using CCI > > > > Add support for routing PCIe DMA traffic coherently when Cache > > Coherent Interconnect (CCI) is enabled in the system. > > The "dma-coherent" property is used to determine if CCI is enabled or n= ot. > > Refer to https://developer.arm.com/documentation/ddi0470/k/preface > > for the CCI specification. > > > > Signed-off-by: Bharat Kumar Gogada > > --- > > drivers/pci/controller/pcie-xilinx-nwl.c | 7 +++++++ > > 1 file changed, 7 insertions(+) > > > > diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c > > b/drivers/pci/controller/pcie-xilinx-nwl.c > > index 07e36661bbc2..8689311c5ef6 100644 > > --- a/drivers/pci/controller/pcie-xilinx-nwl.c > > +++ b/drivers/pci/controller/pcie-xilinx-nwl.c > > @@ -26,6 +26,7 @@ > > > > /* Bridge core config registers */ > > #define BRCFG_PCIE_RX0 0x00000000 > > +#define BRCFG_PCIE_RX1 0x00000004 > > #define BRCFG_INTERRUPT 0x00000010 > > #define BRCFG_PCIE_RX_MSG_FILTER 0x00000020 > > > > @@ -128,6 +129,7 @@ > > #define NWL_ECAM_VALUE_DEFAULT 12 > > > > #define CFG_DMA_REG_BAR GENMASK(2, 0) > > +#define CFG_PCIE_CACHE GENMASK(7, 0) > > > > #define INT_PCI_MSI_NR (2 * 32) > > > > @@ -675,6 +677,11 @@ static int nwl_pcie_bridge_init(struct nwl_pcie > > *pcie) > > nwl_bridge_writel(pcie, CFG_ENABLE_MSG_FILTER_MASK, > > BRCFG_PCIE_RX_MSG_FILTER); > > > > + /* This routes the PCIe DMA traffic to go through CCI path */ > > + if (of_dma_is_coherent(dev->of_node)) > > + nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, > > BRCFG_PCIE_RX1) | > > + CFG_PCIE_CACHE, BRCFG_PCIE_RX1); > > + > > err =3D nwl_wait_for_link(pcie); > > if (err) > > return err; > > -- > > 2.17.1