From: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
To: "Z.q. Hou" <zhiqiang.hou@nxp.com>
Cc: "linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"bhelgaas@google.com" <bhelgaas@google.com>,
"robh+dt@kernel.org" <robh+dt@kernel.org>,
"mark.rutland@arm.com" <mark.rutland@arm.com>,
"shawnguo@kernel.org" <shawnguo@kernel.org>,
Leo Li <leoyang.li@nxp.com>,
"lorenzo.pieralisi@arm.com" <lorenzo.pieralisi@arm.com>,
"catalin.marinas@arm.com" <catalin.marinas@arm.com>,
"will.deacon@arm.com" <will.deacon@arm.com>,
Mingkai Hu <mingkai.hu@nxp.com>,
"M.h. Lian" <minghuan.lian@nxp.com>,
Xiaowei Bao <xiaowei.bao@nxp.com>
Subject: Re: [PATCHv3 25/27] PCI: mobiveil: ls_pcie_g4: add Workaround for A-011451
Date: Fri, 8 Feb 2019 18:23:18 +0530 [thread overview]
Message-ID: <CAFZiPx24PEE6LnUaY5MiQ_QDLbwkF-BvWe8s9ycUDVH-dN2_xg@mail.gmail.com> (raw)
In-Reply-To: <20190129080926.36773-26-Zhiqiang.Hou@nxp.com>
ZQ,
On Tue, Jan 29, 2019 at 1:41 PM Z.q. Hou <zhiqiang.hou@nxp.com> wrote:
>
> From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
>
> When LX2 PCIe controller is sending multiple split completions and
> ACK latency expires indicating that ACK should be send at priority.
> But because of large number of split completions and FC update DLLP,
> the controller does not give priority to ACK transmission. This
> results into ACK latency timer timeout error at the link partner and
> the pending TLPs are replayed by the link partner again.
>
> Workaround:
> 1. Reduce the ACK latency timeout value to a very small value.
> 2. Restrict the number of completions from the LX2 PCIe controller
> to 1, by changing the Max Read Request Size (MRRS) of link partner
> to the same value as Max Packet size (MPS).
>
> This patch implemented part 1, the part 2 can be set by kernel parameter
> 'pci=pcie_bus_perf'
>
> This ERRATA is only for LX2160A Rev1.0, and it will be fixed
> in Rev2.0.
>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---
> V3:
> - Integrated without change from http://patchwork.ozlabs.org/patch/1006796/
>
> .../pci/controller/mobiveil/pci-layerscape-gen4.c | 15 +++++++++++++++
> drivers/pci/controller/mobiveil/pcie-mobiveil.h | 4 ++++
> 2 files changed, 19 insertions(+)
>
> diff --git a/drivers/pci/controller/mobiveil/pci-layerscape-gen4.c b/drivers/pci/controller/mobiveil/pci-layerscape-gen4.c
> index d2c5dbbd5e3c..20ce146788ca 100644
> --- a/drivers/pci/controller/mobiveil/pci-layerscape-gen4.c
> +++ b/drivers/pci/controller/mobiveil/pci-layerscape-gen4.c
> @@ -82,12 +82,27 @@ static bool ls_pcie_g4_is_bridge(struct ls_pcie_g4 *pcie)
> return header_type == PCI_HEADER_TYPE_BRIDGE;
> }
>
> +static void workaround_A011451(struct ls_pcie_g4 *pcie)
> +{
> + struct mobiveil_pcie *mv_pci = pcie->pci;
> + u32 val;
> +
> + /* Set ACK latency timeout */
> + val = csr_readl(mv_pci, GPEX_ACK_REPLAY_TO);
> + val &= ~(ACK_LAT_TO_VAL_MASK << ACK_LAT_TO_VAL_SHIFT);
> + val |= (4 << ACK_LAT_TO_VAL_SHIFT);
> + csr_writel(mv_pci, val, GPEX_ACK_REPLAY_TO);
> +}
> +
> static int ls_pcie_g4_host_init(struct mobiveil_pcie *pci)
> {
> struct ls_pcie_g4 *pcie = to_ls_pcie_g4(pci);
>
> pcie->rev = csr_readb(pci, PCI_REVISION_ID);
>
> + if (pcie->rev == REV_1_0)
> + workaround_A011451(pcie);
> +
> return 0;
> }
>
> diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil.h b/drivers/pci/controller/mobiveil/pcie-mobiveil.h
> index ab43de5e4b2b..f0e2e4ae09b5 100644
> --- a/drivers/pci/controller/mobiveil/pcie-mobiveil.h
> +++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.h
> @@ -85,6 +85,10 @@
> #define PAB_AXI_AMAP_PEX_WIN_H(win) PAB_REG_ADDR(0x0bac, win)
> #define PAB_INTP_AXI_PIO_CLASS 0x474
>
> +#define GPEX_ACK_REPLAY_TO 0x438
> +#define ACK_LAT_TO_VAL_MASK 0x1fff
> +#define ACK_LAT_TO_VAL_SHIFT 0
> +
> #define PAB_PEX_AMAP_CTRL(win) PAB_REG_ADDR(0x4ba0, win)
> #define AMAP_CTRL_EN_SHIFT 0
> #define AMAP_CTRL_TYPE_SHIFT 1
> --
> 2.17.1
>
again, can we avoid errata number on patch title and have a brief title instead?
next prev parent reply other threads:[~2019-02-08 12:50 UTC|newest]
Thread overview: 68+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-01-29 8:08 [PATCHv3 00/27] PCI: refactor Mobiveil driver and add PCIe Gen4 driver for NXP Layerscape SoCs Z.q. Hou
2019-01-29 8:08 ` [PATCHv3 01/27] PCI: mobiveil: uniform the register accessors Z.q. Hou
2019-02-05 5:39 ` Subrahmanya Lingappa
2019-02-05 17:43 ` Lorenzo Pieralisi
2019-02-06 10:59 ` Subrahmanya Lingappa
2019-01-29 8:08 ` [PATCHv3 02/27] PCI: mobiveil: format the code without function change Z.q. Hou
2019-02-05 5:48 ` Subrahmanya Lingappa
2019-02-18 7:03 ` Z.q. Hou
2019-01-29 8:08 ` [PATCHv3 03/27] PCI: mobiveil: correct the returned error number Z.q. Hou
2019-02-05 5:53 ` Subrahmanya Lingappa
2019-01-29 8:08 ` [PATCHv3 04/27] PCI: mobiveil: remove flag MSI_FLAG_MULTI_PCI_MSI Z.q. Hou
2019-02-05 6:05 ` Subrahmanya Lingappa
2019-02-18 7:03 ` Z.q. Hou
2019-01-29 8:09 ` [PATCHv3 05/27] PCI: mobiveil: correct PCI base address in MEM/IO outbound windows Z.q. Hou
2019-02-05 6:06 ` Subrahmanya Lingappa
2019-01-29 8:09 ` [PATCHv3 06/27] PCI: mobiveil: replace the resource list iteration function Z.q. Hou
2019-02-05 6:07 ` Subrahmanya Lingappa
2019-01-29 8:09 ` [PATCHv3 07/27] PCI: mobiveil: use WIN_NUM_0 explicitly for CFG outbound window Z.q. Hou
2019-02-05 6:08 ` Subrahmanya Lingappa
2019-01-29 8:09 ` [PATCHv3 08/27] PCI: mobiveil: use the 1st inbound window for MEM inbound transactions Z.q. Hou
2019-02-05 6:08 ` Subrahmanya Lingappa
2019-01-29 8:09 ` [PATCHv3 09/27] PCI: mobiveil: correct inbound/outbound window setup routines Z.q. Hou
2019-02-05 6:10 ` Subrahmanya Lingappa
2019-02-18 7:07 ` Z.q. Hou
2019-01-29 8:09 ` [PATCHv3 10/27] PCI: mobiveil: fix the INTx process error Z.q. Hou
2019-02-05 6:11 ` Subrahmanya Lingappa
2019-01-29 8:09 ` [PATCHv3 11/27] PCI: mobiveil: only fix up the Class Code field Z.q. Hou
2019-02-05 6:11 ` Subrahmanya Lingappa
2019-01-29 8:09 ` [PATCHv3 12/27] PCI: mobiveil: move out the link up waiting from mobiveil_host_init Z.q. Hou
2019-02-05 6:12 ` Subrahmanya Lingappa
2019-01-29 8:09 ` [PATCHv3 13/27] PCI: mobiveil: move irq chained handler setup out of DT parse Z.q. Hou
2019-02-08 12:30 ` Subrahmanya Lingappa
2019-01-29 8:09 ` [PATCHv3 14/27] PCI: mobiveil: initialize Primary/Secondary/Subordinate bus number Z.q. Hou
2019-02-08 12:31 ` Subrahmanya Lingappa
2019-01-29 8:10 ` [PATCHv3 15/27] dt-bindings: pci: mobiveil: change gpio_slave and apb_csr to optional Z.q. Hou
2019-02-08 12:32 ` Subrahmanya Lingappa
2019-01-29 8:10 ` [PATCHv3 16/27] PCI: mobiveil: refactor Mobiveil PCIe Host Bridge IP driver Z.q. Hou
2019-02-08 12:37 ` Subrahmanya Lingappa
2019-01-29 8:10 ` [PATCHv3 17/27] PCI: mobiveil: fix the checking of valid device Z.q. Hou
2019-02-08 12:41 ` Subrahmanya Lingappa
2019-02-08 14:13 ` Bjorn Helgaas
2019-02-18 7:15 ` Z.q. Hou
2019-02-18 7:04 ` Z.q. Hou
2019-01-29 8:10 ` [PATCHv3 18/27] PCI: mobiveil: continue to initialize the host upon no PCIe link Z.q. Hou
2019-02-08 12:41 ` Subrahmanya Lingappa
2019-01-29 8:10 ` [PATCHv3 19/27] PCI: mobiveil: disabled IB and OB windows set by bootloader Z.q. Hou
2019-02-08 12:42 ` Subrahmanya Lingappa
2019-01-29 8:10 ` [PATCHv3 20/27] PCI: mobiveil: add Byte and Half-Word width register accessors Z.q. Hou
2019-02-08 12:44 ` Subrahmanya Lingappa
2019-01-29 8:10 ` [PATCHv3 21/27] PCI: mobiveil: make mobiveil_host_init can be used to re-init host Z.q. Hou
2019-02-08 12:46 ` Subrahmanya Lingappa
2019-01-29 8:10 ` [PATCHv3 22/27] dt-bindings: pci: Add NXP Layerscape SoCs PCIe Gen4 controller Z.q. Hou
2019-01-30 18:49 ` Rob Herring
2019-01-29 8:10 ` [PATCHv3 23/27] PCI: mobiveil: add PCIe Gen4 RC driver for NXP Layerscape SoCs Z.q. Hou
2019-02-08 12:49 ` Subrahmanya Lingappa
2019-02-18 7:05 ` Z.q. Hou
2019-01-29 8:11 ` [PATCHv3 24/27] PCI: mobiveil: ls_pcie_g4: add Workaround for A-011577 Z.q. Hou
2019-02-08 12:52 ` Subrahmanya Lingappa
2019-02-18 7:10 ` Z.q. Hou
2019-01-29 8:11 ` [PATCHv3 25/27] PCI: mobiveil: ls_pcie_g4: add Workaround for A-011451 Z.q. Hou
2019-02-08 12:53 ` Subrahmanya Lingappa [this message]
2019-02-18 7:14 ` Z.q. Hou
2019-01-29 8:11 ` [PATCHv3 26/27] arm64: dts: freescale: lx2160a: add pcie DT nodes Z.q. Hou
2019-01-29 8:11 ` [PATCHv3 27/27] arm64: defconfig: Enable CONFIG_PCI_LAYERSCAPE_GEN4 Z.q. Hou
2019-01-29 11:39 ` [PATCHv3 00/27] PCI: refactor Mobiveil driver and add PCIe Gen4 driver for NXP Layerscape SoCs Lorenzo Pieralisi
[not found] ` <CAFZiPx002HED+YH2GysS7a7uoEDQuHGjxa_CQtwb9nSDH-XNuA@mail.gmail.com>
2019-02-04 16:13 ` Lorenzo Pieralisi
2019-02-04 16:51 ` Subrahmanya Lingappa
2019-01-30 15:34 ` Bjorn Helgaas
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