Re: [PATCH] dt-bindings: PCI: xilinx-cpm: Change reg property order

From: Rob Herring <robh@kernel.org>
To: Michal Simek <michal.simek@xilinx.com>
Cc: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>,
	PCI <linux-pci@vger.kernel.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	devicetree@vger.kernel.org,
	Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
	Bjorn Helgaas <bhelgaas@google.com>
Subject: Re: [PATCH] dt-bindings: PCI: xilinx-cpm: Change reg property order
Date: Tue, 10 May 2022 11:00:07 -0500	[thread overview]
Message-ID: <CAL_JsqJj_CPPn9+by3rSpSXW9ufUcbsUbNbE3wE5qFRrJ-PjKg@mail.gmail.com> (raw)
In-Reply-To: <eea7db0b-b483-e61c-8f2d-174f2032fd51@xilinx.com>

On Tue, May 10, 2022 at 2:29 AM Michal Simek <michal.simek@xilinx.com> wrote:
>
>
>
> On 5/4/22 17:43, Rob Herring wrote:
> > On Fri, Apr 29, 2022 at 8:02 AM Bharat Kumar Gogada
> > <bharat.kumar.gogada@xilinx.com> wrote:
> >>
> >> Describe cpm reg property before cfg reg property to align with
> >> node name.
> >
> > The order is an ABI. If breaking it is okay, explain why here.
>
> I didn't push any description for versal to upstream u-boot or linux yet but
> xilinx is using this order for years. DT binding order wasn't aligned to it.
>
> For example: (Xilinx Linux is in sync with this).
> https://github.com/Xilinx/u-boot-xlnx/blob/master/arch/arm/dts/versal.dtsi

Good to know, but if there are upstream dts files, what do they use?

> Driver itself is working with reg-names and order of regs doesn't matter. It
> means changed order doesn't break any functionality.

While in general I consider the order part of the ABI, if that's
enough to avoid breakage on anything you care about, then just state
that.

> Right now reg order really matter in binding doc but would be good in these
> examples to record that both ways are fine.
> Would it be better to describe that both ways are fine?

Only if that's what you need. If you are fine with the order changing,
then make the change and fix all the dts files.

>
>    reg-names:
>      oneOf:
>      - items:
>        - const: cfg
>        - const: cpm_slcr
>      - items:
>        - const: cpm_slcr
>        - const: cfg
>
>
> Another small reason is that all hard IPs in Versal are normally placed below
> 4GB address range. And there are some others which also have mapping above. This
> is one of that example and we normally aligned with 32bit address.
>
> And the biggest reason is that current node name is pcie@fca10000 which should
> be aligned with the first register base which is before this patch 0x600000000
> but name suggest that the first reg should be cpm_slcr instead of cfg. That's
> why I consider this patch as a fix and the patch should contain fixed tag.

I don't disagree. I'm only asking for a better commit message.

Rob