From: Johan Hovold <johan@kernel.org>
To: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Cc: "Andy Gross" <agross@kernel.org>,
"Bjorn Andersson" <bjorn.andersson@linaro.org>,
"Stanimir Varbanov" <svarbanov@mm-sol.com>,
"Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Michael Turquette" <mturquette@baylibre.com>,
"Stephen Boyd" <swboyd@chromium.org>,
"Johan Hovold" <johan+linaro@kernel.org>,
"Manivannan Sadhasivam" <manivannan.sadhasivam@linaro.org>,
"Prasad Malisetty" <pmaliset@codeaurora.org>,
"Vinod Koul" <vkoul@kernel.org>,
linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org,
linux-clk@vger.kernel.org
Subject: Re: [PATCH v5 0/5] PCI: qcom: Rework pipe_clk/pipe_clk_src handling
Date: Fri, 13 May 2022 09:41:36 +0200 [thread overview]
Message-ID: <Yn4LsB/dkwjdslQs@hovoldconsulting.com> (raw)
In-Reply-To: <20220512172909.2436302-1-dmitry.baryshkov@linaro.org>
On Thu, May 12, 2022 at 08:29:04PM +0300, Dmitry Baryshkov wrote:
> PCIe pipe clk (and some other clocks) must be parked to the "safe"
> source (bi_tcxo) when corresponding GDSC is turned off and on again.
> Currently this is handcoded in the PCIe driver by reparenting the
> gcc_pipe_N_clk_src clock.
>
> Instead of doing it manually, follow the approach used by
> clk_rcg2_shared_ops and implement this parking in the enable() and
> disable() clock operations for respective pipe clocks.
>
> PCIe part depends on [1].
This one was merged a month ago.
> Changes since v4:
> - Renamed the clock to clk-regmap-pipe-src,
> - Added mention of PCIe2 PHY to the commit message,
> - Expanded commit messages to mention additional pipe clock details.
>
> Changes since v3:
> - Replaced the clock multiplexer implementation with branch-like clock.
>
> Changes since v2:
> - Added is_enabled() callback
> - Added default parent to the pipe clock configuration
>
> Changes since v1:
> - Rebased on top of [1].
> - Removed erroneous Fixes tag from the patch 4.
>
> Changes since RFC:
> - Rework clk-regmap-mux fields. Specify safe parent as P_* value rather
> than specifying the register value directly
> - Expand commit message to the first patch to specially mention that
> it is required only on newer generations of Qualcomm chipsets.
>
> [1]: https://lore.kernel.org/all/20220401133351.10113-1-johan+linaro@kernel.org/
Johan
next prev parent reply other threads:[~2022-05-13 7:41 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-12 17:29 [PATCH v5 0/5] PCI: qcom: Rework pipe_clk/pipe_clk_src handling Dmitry Baryshkov
2022-05-12 17:29 ` [PATCH v5 1/5] PCI: qcom: Remove unnecessary pipe_clk handling Dmitry Baryshkov
2022-05-13 7:45 ` Johan Hovold
2022-05-12 17:29 ` [PATCH v5 2/5] clk: qcom: regmap: add PHY clock source implementation Dmitry Baryshkov
2022-05-13 8:16 ` Johan Hovold
2022-05-13 9:50 ` Dmitry Baryshkov
2022-05-12 17:29 ` [PATCH v5 3/5] clk: qcom: gcc-sm8450: use new clk_regmap_pipe_src_ops for PCIe pipe clocks Dmitry Baryshkov
2022-05-12 17:29 ` [PATCH v5 4/5] clk: qcom: gcc-sc7280: " Dmitry Baryshkov
2022-05-12 17:29 ` [PATCH v5 5/5] PCI: qcom: Drop manual pipe_clk_src handling Dmitry Baryshkov
2022-05-13 8:19 ` Johan Hovold
2022-05-13 7:41 ` Johan Hovold [this message]
2022-05-13 9:31 ` [PATCH v5 0/5] PCI: qcom: Rework pipe_clk/pipe_clk_src handling Dmitry Baryshkov
2022-05-13 9:43 ` Johan Hovold
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