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From: Ira Weiny <ira.weiny@intel.com>
To: Ben Widawsky <bwidawsk@kernel.org>
Cc: Dan Williams <dan.j.williams@intel.com>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Jonathan Cameron <Jonathan.Cameron@huawei.com>,
	Alison Schofield <alison.schofield@intel.com>,
	Davidlohr Bueso <dave@stgolabs.net>,
	Vishal Verma <vishal.l.verma@intel.com>,
	Dave Jiang <dave.jiang@intel.com>, <linux-kernel@vger.kernel.org>,
	<linux-cxl@vger.kernel.org>, <linux-pci@vger.kernel.org>
Subject: Re: [PATCH V10 8/9] cxl/port: Retry reading CDAT on failure
Date: Wed, 8 Jun 2022 16:07:12 -0700	[thread overview]
Message-ID: <YqEroOuHpEa2GkHA@iweiny-desk3> (raw)
In-Reply-To: <20220606185203.ntm3yf73kf4u2o7a@bwidawsk-mobl5>

On Mon, Jun 06, 2022 at 11:52:03AM -0700, Ben Widawsky wrote:
> On 22-06-04 17:50:48, ira.weiny@intel.com wrote:
> > From: Ira Weiny <ira.weiny@intel.com>
> > 
> > The CDAT read may fail for a number of reasons but mainly it is possible
> > to get different parts of a valid state.  The checksum in the CDAT table
> > protects against this.
> > 
> > Now that the cdat data is validated issue a retries if the CDAT read
> s/validated issue a retries/validated, issue a retry/

Thanks!

> > fails.  For now 5 retries are implemented.
> > 
> > Cc: Alison Schofield <alison.schofield@intel.com>
> > Cc: Davidlohr Bueso <dave@stgolabs.net>
> > Signed-off-by: Ira Weiny <ira.weiny@intel.com>
> > 
> > ---
> > Changes from V9
> > 	Alison Schofield/Davidlohr Bueso
> > 		Print debug on each iteration and error only after failure
> > 
> > Changes from V8
> > 	Move code to cxl/core/pci.c
> > 
> > Changes from V6
> > 	Move to pci.c
> > 	Fix retries count
> > 	Change to 5 retries
> > 
> > Changes from V5:
> > 	New patch -- easy to push off or drop.
> > ---
> >  drivers/cxl/core/pci.c | 34 +++++++++++++++++++++++-----------
> >  1 file changed, 23 insertions(+), 11 deletions(-)
> > 
> > diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
> > index 73e28b82ffcf..e68f13e66fcf 100644
> > --- a/drivers/cxl/core/pci.c
> > +++ b/drivers/cxl/core/pci.c
> > @@ -631,20 +631,18 @@ static int cxl_cdat_read_table(struct cxl_port *port,
> >  	return rc;
> >  }
> >  
> > -void read_cdat_data(struct cxl_port *port)
> > +static int __read_cdat_data(struct cxl_port *port)
> >  {
> >  	struct device *dev = &port->dev;
> >  	size_t cdat_length;
> >  	int ret;
> >  
> >  	if (cxl_cdat_get_length(port, &cdat_length))
> > -		return;
> > +		return 0;
> >  
> >  	port->cdat.table = devm_kzalloc(dev, cdat_length, GFP_KERNEL);
> > -	if (!port->cdat.table) {
> > -		ret = -ENOMEM;
> > -		goto error;
> > -	}
> > +	if (!port->cdat.table)
> > +		return -ENOMEM;
> >  
> >  	port->cdat.length = cdat_length;
> >  	ret = cxl_cdat_read_table(port, &port->cdat);
> > @@ -652,12 +650,26 @@ void read_cdat_data(struct cxl_port *port)
> >  		devm_kfree(dev, port->cdat.table);
> >  		port->cdat.table = NULL;
> >  		port->cdat.length = 0;
> > -		ret = -EIO;
> > -		goto error;
> > +		return -EIO;
> >  	}
> >  
> > -	return;
> > -error:
> > -	dev_err(dev, "CDAT data read error (%d)\n", ret);
> > +	return 0;
> > +}
> > +
> > +void read_cdat_data(struct cxl_port *port)
> > +{
> > +	int retries = 5;
> > +	int rc;
> > +
> > +	while (retries--) {
> > +		rc = __read_cdat_data(port);
> > +		if (!rc)
> > +			return;
> > +		dev_dbg(&port->dev,
> > +			"CDAT data read error rc=%d (retries %d)\n",
> > +			rc, retries);
> 
> Out of curiousity, what is the purpose of the dev_dbg? To diagnose delays or
> something?

Yes

> 
> > +	}
> > +	dev_err(&port->dev, "CDAT data read failed after %d retries\n",
> > +		retries);
> 
> 
> Reviewed-by: Ben Widawsky <bwidawsk@kernel.org>

Thanks!
Ira

> 
> >  }
> >  EXPORT_SYMBOL_NS_GPL(read_cdat_data, CXL);
> > -- 
> > 2.35.1
> > 

  reply	other threads:[~2022-06-08 23:07 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-06-05  0:50 [PATCH V10 0/9] CXL: Read CDAT and DSMAS data ira.weiny
2022-06-05  0:50 ` [PATCH V10 1/9] PCI: Add vendor ID for the PCI SIG ira.weiny
2022-06-05  0:50 ` [PATCH V10 2/9] PCI: Replace magic constant for PCI Sig Vendor ID ira.weiny
2022-06-05  0:50 ` [PATCH V10 3/9] PCI: Create PCI library functions in support of DOE mailboxes ira.weiny
2022-06-20  8:39   ` Zhuo, Qiuxu
2022-06-20 21:46     ` Ira Weiny
2022-06-05  0:50 ` [PATCH V10 4/9] cxl/pci: Create PCI DOE mailbox's for memory devices ira.weiny
2022-06-06 17:42   ` Ben Widawsky
2022-06-05  0:50 ` [PATCH V10 5/9] cxl/port: Find a DOE mailbox which supports CDAT ira.weiny
2022-06-06 17:48   ` Ben Widawsky
2022-06-08 19:39     ` Ira Weiny
2022-06-08 21:38       ` Ira Weiny
2022-06-05  0:50 ` [PATCH V10 6/9] cxl/port: Read CDAT table ira.weiny
2022-06-06 18:15   ` Ben Widawsky
2022-06-08 21:27     ` Ira Weiny
2022-06-09  8:27       ` Jonathan Cameron
2022-06-09 22:03         ` Ira Weiny
2022-06-05  0:50 ` [PATCH V10 7/9] cxl/port: Introduce cxl_cdat_valid() ira.weiny
2022-06-05  0:50 ` [PATCH V10 8/9] cxl/port: Retry reading CDAT on failure ira.weiny
2022-06-06 18:52   ` Ben Widawsky
2022-06-08 23:07     ` Ira Weiny [this message]
2022-06-05  0:50 ` [PATCH V10 9/9] cxl/port: Parse out DSMAS data from CDAT table ira.weiny
2022-06-06 19:32   ` Ben Widawsky
2022-06-09  0:34     ` Ira Weiny

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