From: Stanimir Varbanov <svarbanov@mm-sol.com>
To: Marc Gonzalez <marc.w.gonzalez@free.fr>,
Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Jeffrey Hugo <jhugo@codeaurora.org>,
Vivek Gautam <vivek.gautam@codeaurora.org>,
MSM <linux-arm-msm@vger.kernel.org>,
PCI <linux-pci@vger.kernel.org>
Subject: Re: [PATCH v3] arm64: dts: qcom: msm8998: Add PCIe PHY and RC nodes
Date: Thu, 11 Apr 2019 12:23:32 +0300 [thread overview]
Message-ID: <a435823e-a5e1-a55c-9040-f494de21323c@mm-sol.com> (raw)
In-Reply-To: <c41c4057-8352-3b8e-1bdb-631df1ec3cd8@free.fr>
Hi Marc,
On 4/11/19 11:50 AM, Marc Gonzalez wrote:
> Add MSM8998 PCIe QMP PHY and PCIe root complex DT nodes.
>
> Based on the following DTS downstream:
> https://source.codeaurora.org/quic/la/kernel/msm-4.4/tree/arch/arm/boot/dts/qcom/msm8998.dtsi?h=LE.UM.1.3.r3.25#n2537
>
> Signed-off-by: Marc Gonzalez <marc.w.gonzalez@free.fr>
> ---
> Changes from v2:
> - Move all X-names props *after* corresponding X(s) prop
> - Drop comments
> ---
> arch/arm64/boot/dts/qcom/msm8998.dtsi | 69 +++++++++++++++++++++++++++
> 1 file changed, 69 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi
> index f807ea3e2c6e..dab3333e21f4 100644
> --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi
> +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi
> @@ -621,6 +621,75 @@
> <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>;
> };
>
> + pcie0: pci@1c00000 {
> + compatible = "qcom,pcie-msm8996";
> + reg = <0x01c00000 0x2000>,
> + <0x1b000000 0xf1d>,
> + <0x1b000f20 0xa8>,
> + <0x1b100000 0x100000>;
> + reg-names = "parf", "dbi", "elbi", "config";
> + device_type = "pci";
> + linux,pci-domain = <0>;
> + bus-range = <0x00 0xff>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> + num-lanes = <1>;
> + phys = <&pciephy>;
> + phy-names = "pciephy";
> +
> + ranges = <0x01000000 0x0 0x1b200000 0x1b200000 0x0 0x100000>,
> + <0x02000000 0x0 0x1b300000 0x1b300000 0x0 0xd00000>;
> +
> + #interrupt-cells = <1>;
> + interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "msi";
> + interrupt-map-mask = <0 0 0 0x7>;
> + interrupt-map = <0 0 0 1 &intc 0 135 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 2 &intc 0 136 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 3 &intc 0 138 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 4 &intc 0 139 IRQ_TYPE_LEVEL_HIGH>;
> +
> + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
> + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
> + <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
> + <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
> + <&gcc GCC_PCIE_0_AUX_CLK>;
> + clock-names = "pipe", "bus_master", "bus_slave", "cfg", "aux";
> +
> + power-domains = <&gcc PCIE_0_GDSC>;
> + iommu-map = <0x100 &anoc1_smmu 0x1480 1>;
> + perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
where are pinctrl properties? Probably in board .dts files?
--
regards,
Stan
next prev parent reply other threads:[~2019-04-11 9:23 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-04-09 12:11 [PATCH v2] arm64: dts: qcom: msm8998: Add PCIe PHY and RC nodes Marc Gonzalez
2019-04-11 8:50 ` [PATCH v3] " Marc Gonzalez
2019-04-11 9:23 ` Stanimir Varbanov [this message]
2019-04-11 9:46 ` Marc Gonzalez
2019-04-11 14:55 ` Marc Gonzalez
2019-06-17 15:53 ` Bjorn Andersson
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