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[86.49.35.8]) by smtp.gmail.com with ESMTPSA id l22sm10686043wrb.45.2019.10.26.11.06.39 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 26 Oct 2019 11:06:39 -0700 (PDT) Subject: Re: [PATCH V3 2/3] PCI: rcar: Do not abort on too many inbound dma-ranges To: Andrew Murray Cc: Simon Horman , linux-pci@vger.kernel.org, Marek Vasut , Geert Uytterhoeven , Lorenzo Pieralisi , Wolfram Sang , linux-renesas-soc@vger.kernel.org References: <20190809175741.7066-1-marek.vasut@gmail.com> <20190809175741.7066-2-marek.vasut@gmail.com> <20190816132305.gyyml5r3xsimmoor@verge.net.au> <8f1871ed-4820-1985-0090-bb9e2d8803d8@gmail.com> <20191021101805.GM47056@e119886-lin.cambridge.arm.com> From: Marek Vasut Message-ID: Date: Sat, 26 Oct 2019 20:03:12 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.9.0 MIME-Version: 1.0 In-Reply-To: <20191021101805.GM47056@e119886-lin.cambridge.arm.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On 10/21/19 12:18 PM, Andrew Murray wrote: [...] >>>> In case the "dma-ranges" DT property contains either too many ranges >>>> or the range start address is unaligned in such a way that populating >>>> the range into the controller requires multiple entries, a situation >>>> may occur where all ranges cannot be loaded into the controller. >>>> >>>> Currently, the driver refuses to probe in such a situation. Relax this >>>> behavior, load as many ranges as possible and warn if some ranges do >>>> not fit anymore. >>> >>> What is the motivation for relaxing this? >> >> U-Boot can fill the ranges in properly now, the list would be longer in >> such a case and the driver would fail to probe (because the list is >> longer than what the hardware can support). > > Is this the U-Boot patch you refer to: > > https://patchwork.ozlabs.org/patch/1129436/ Yes. > As pci_set_region is called with the same address for PCI and CPU memory > this implies there is a 1:1 mapping - therefore I don't see a need for > multiple mappings for each DRAM bank. (Also if this controller has a > 32 bit limitation, shouldn't this code limit the addresses before calling > pci_set_region?). It would certainly be helpful to know about this dma-ranges detail earlier, this whole thing could've been avoided. Now all I can do is get that patch reverted for the next U-Boot release. But this still leaves me with one open question -- how do I figure out what to program into the PCI controller inbound windows, so that the controller correctly filters inbound transfers which are targetting nonexisting memory ? -- Best regards, Marek Vasut