linux-pm.vger.kernel.org archive mirror
 help / color / mirror / Atom feed
From: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
To: "Rafael J. Wysocki" <rafael@kernel.org>,
	Doug Smythies <dsmythies@telus.net>
Cc: "Rafael J. Wysocki" <rjw@rjwysocki.net>,
	Linux Documentation <linux-doc@vger.kernel.org>,
	LKML <linux-kernel@vger.kernel.org>,
	Peter Zijlstra <peterz@infradead.org>,
	Giovanni Gherdovich <ggherdovich@suse.cz>,
	Francisco Jerez <francisco.jerez.plata@intel.com>,
	Viresh Kumar <viresh.kumar@linaro.org>,
	Linux PM <linux-pm@vger.kernel.org>
Subject: Re: [PATCH v6] cpufreq: intel_pstate: Implement passive mode with HWP enabled
Date: Wed, 05 Aug 2020 08:38:33 -0700	[thread overview]
Message-ID: <ff21e71060b589219c21b46b5e26b6c3aca9f951.camel@linux.intel.com> (raw)
In-Reply-To: <CAJZ5v0h7iKvO1-9R_JiVjM8j_a87B=LpTCoaUWRfrhXTRaMMOw@mail.gmail.com>

On Wed, 2020-08-05 at 11:34 +0200, Rafael J. Wysocki wrote:
> Hi Doug,
> 
> On Tue, Aug 4, 2020 at 7:07 PM Doug Smythies <dsmythies@telus.net>
> wrote:
> > Hi Rafael,
> > 
> > 
[...]

> Note that the active mode performance scaling algorithm (which is not
> the same as the performance cpufreq governor) sets the EPP to 0 for
> all of the CPUs that it is used with and the driver sets the EPP to
> 255 in ->stop_cpu.
> 
> That last bit is questionable, but that's the active mode behavior
> which is not changed by the $subject patch.
You need to set the CPU which is going offline to the lowest perf
settings. If not its sibling's performance can never be lowered than
offlined CPUs max/min/epp.

Thanks,
Srinivas


> 
> It would be more reasonable to restore the previous EPP when stopping
> CPUs.  Let me cut a v7 with that changed.
> 
> > # /home/doug/c/msr-decoder
> > How many CPUs?: 6
> > 8.) 0x198: IA32_PERF_STATUS     : CPU 0-5 :  46 :  46 :  46 :  46
> > :  46 :  46 :
> > B.) 0x770: IA32_PM_ENABLE: 1 : HWP enable
> > 1.) 0x19C: IA32_THERM_STATUS: 88450000
> > 2.) 0x1AA: MSR_MISC_PWR_MGMT: 401CC0 EIST enabled Coordination
> > enabled OOB Bit 8 reset OOB Bit 18 reset
> > 3.) 0x1B1: IA32_PACKAGE_THERM_STATUS: 88430000
> > 4.) 0x64F: MSR_CORE_PERF_LIMIT_REASONS: 0
> > A.) 0x1FC: MSR_POWER_CTL: 3C005D : C1E disable : EEO disable : RHO
> > disable
> > 5.) 0x771: IA32_HWP_CAPABILITIES (performance): 109252E : high 46 :
> > guaranteed 37 : efficient 9 : lowest 1
> > 6.) 0x774: IA32_HWP_REQUEST:    CPU 0-5 :
> >     raw: 00002E2E : 00002E2E : 00002E2E : 00002E2E : 00002E2E :
> > 00002E2E :
> >     min:       46 :       46 :       46 :       46 :       46
> > :       46 :
> >     max:       46 :       46 :       46 :       46 :       46
> > :       46 :
> >     des:        0 :        0 :        0 :        0 :        0
> > :        0 :
> >     epp:        0 :        0 :        0 :        0 :        0
> > :        0 :
> >     act:        0 :        0 :        0 :        0 :        0
> > :        0 :
> > 7.) 0x777: IA32_HWP_STATUS: 4 : high 4 : guaranteed 0 : efficient 0
> > : lowest 0
> > 
> > and then switched to passive mode later. EPP is not as expected.
> > Expect 0
> > (performance mode):
> > 
> > # /home/doug/c/msr-decoder
> > How many CPUs?: 6
> > 8.) 0x198: IA32_PERF_STATUS     : CPU 0-5 :  46 :  46 :  46 :  46
> > :  46 :  46 :
> > B.) 0x770: IA32_PM_ENABLE: 1 : HWP enable
> > 1.) 0x19C: IA32_THERM_STATUS: 88440000
> > 2.) 0x1AA: MSR_MISC_PWR_MGMT: 401CC0 EIST enabled Coordination
> > enabled OOB Bit 8 reset OOB Bit 18 reset
> > 3.) 0x1B1: IA32_PACKAGE_THERM_STATUS: 88420000
> > 4.) 0x64F: MSR_CORE_PERF_LIMIT_REASONS: 0
> > A.) 0x1FC: MSR_POWER_CTL: 3C005D : C1E disable : EEO disable : RHO
> > disable
> > 5.) 0x771: IA32_HWP_CAPABILITIES (performance): 108252E : high 46 :
> > guaranteed 37 : efficient 8 : lowest 1
> > 6.) 0x774: IA32_HWP_REQUEST:    CPU 0-5 :
> >     raw: FF002E2E : FF002E2E : FF002E2E : FF002E2E : FF002E2E :
> > FF002E2E :
> >     min:       46 :       46 :       46 :       46 :       46
> > :       46 :
> >     max:       46 :       46 :       46 :       46 :       46
> > :       46 :
> >     des:        0 :        0 :        0 :        0 :        0
> > :        0 :
> >     epp:      255 :      255 :      255 :      255 :      255
> > :      255 :
> >     act:        0 :        0 :        0 :        0 :        0
> > :        0 :
> > 7.) 0x777: IA32_HWP_STATUS: 4 : high 4 : guaranteed 0 : efficient 0
> > : lowest 0
> 
> The 0xFF EPP value is what the active mode left behind and the
> passive
> mode doesn't touch the EPP at all.
> 
> > Then switched to ondemand governor, and put 100% load on 2 CPUs.
> > EPP is not as expected, which I don't actually know what to expect,
> > but assume 128:
> > 
> > # /home/doug/c/msr-decoder
> > How many CPUs?: 6
> > 8.) 0x198: IA32_PERF_STATUS     : CPU 0-5 :  46 :  46 :  46 :  46
> > :  46 :  46 :
> > B.) 0x770: IA32_PM_ENABLE: 1 : HWP enable
> > 1.) 0x19C: IA32_THERM_STATUS: 883B0000
> > 2.) 0x1AA: MSR_MISC_PWR_MGMT: 401CC0 EIST enabled Coordination
> > enabled OOB Bit 8 reset OOB Bit 18 reset
> > 3.) 0x1B1: IA32_PACKAGE_THERM_STATUS: 882B0000
> > 4.) 0x64F: MSR_CORE_PERF_LIMIT_REASONS: 0
> > A.) 0x1FC: MSR_POWER_CTL: 3C005D : C1E disable : EEO disable : RHO
> > disable
> > 5.) 0x771: IA32_HWP_CAPABILITIES (performance): 10B252E : high 46 :
> > guaranteed 37 : efficient 11 : lowest 1
> > 6.) 0x774: IA32_HWP_REQUEST:    CPU 0-5 :
> >     raw: FF002E09 : FF002E0C : FF002E2E : FF002E08 : FF002E2E :
> > FF002E18 :
> >     min:        9 :       12 :       46 :        8 :       46
> > :       24 :
> >     max:       46 :       46 :       46 :       46 :       46
> > :       46 :
> >     des:        0 :        0 :        0 :        0 :        0
> > :        0 :
> >     epp:      255 :      255 :      255 :      255 :      255
> > :      255 :
> >     act:        0 :        0 :        0 :        0 :        0
> > :        0 :
> > 7.) 0x777: IA32_HWP_STATUS: 4 : high 4 : guaranteed 0 : efficient 0
> > : lowest 0
> 
> It is still 0xFF as previously (because the passive mode doesn't
> change the EPP).
> 
> > For what it's worth, Kernel:
> > 
> > 78b39581ed85 (HEAD -> dtemp) cpufreq: intel_pstate: Implement
> > passive mode with HWP enabled
> > c0842fbc1b18 (origin/master, origin/HEAD, master) random32: move
> > the pseudo-random 32-bit definitions to prandom.h
> > 2baa85d6927d Merge tag 'acpi-5.9-rc1' of
> > git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm
> > 04084978003c Merge tag 'pm-5.9-rc1' of
> > git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm
> 
> Thanks!


  reply	other threads:[~2020-08-05 20:07 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-07-16 17:37 [PATCH v2 0/2] cpufreq: intel_pstate: Implement passive mode with HWP enabled Rafael J. Wysocki
2020-07-16 17:38 ` [PATCH v2 1/2] cpufreq: intel_pstate: Rearrange the storing of newv EPP values Rafael J. Wysocki
2020-07-16 17:42 ` [PATCH v2 2/2] cpufreq: intel_pstate: Implement passive mode with HWP enabled Rafael J. Wysocki
2020-07-27 15:13 ` [PATCH v3 0/2] " Rafael J. Wysocki
2020-07-27 15:15   ` [PATCH v3 1/2] cpufreq: intel_pstate: Rearrange the storing of new EPP values Rafael J. Wysocki
2020-07-27 15:17   ` [PATCH v3 2/2] cpufreq: intel_pstate: Implement passive mode with HWP enabled Rafael J. Wysocki
2020-07-28 15:09   ` [PATCH v4 0/2] " Rafael J. Wysocki
2020-07-28 15:11     ` [PATCH v4 1/2] cpufreq: intel_pstate: Rearrange the storing of new EPP values Rafael J. Wysocki
2020-07-30  1:31       ` Francisco Jerez
2020-07-28 15:13     ` [PATCH v4 2/2] cpufreq: intel_pstate: Implement passive mode with HWP enabled Rafael J. Wysocki
2020-08-01 23:21       ` Srinivas Pandruvada
2020-08-02 14:14         ` Doug Smythies
2020-08-02 19:20           ` Srinivas Pandruvada
2020-08-03 17:17       ` [PATCH v5] " Rafael J. Wysocki
2020-08-01 16:39     ` [PATCH v4 0/2] " Srinivas Pandruvada
2020-08-02 14:00       ` Doug Smythies
2020-08-02 18:39         ` Srinivas Pandruvada
2020-08-03  0:26           ` Doug Smythies
2020-08-03 17:23       ` Rafael J. Wysocki
2020-08-04 15:10   ` [PATCH v6] " Rafael J. Wysocki
2020-08-04 17:04     ` Doug Smythies
2020-08-05  9:34       ` Rafael J. Wysocki
2020-08-05 15:38         ` Srinivas Pandruvada [this message]
2020-08-05 16:28           ` Rafael J. Wysocki
2020-08-05 16:55   ` [PATCH v7] " Rafael J. Wysocki
2020-08-06  5:55     ` Doug Smythies
2020-08-06 11:25       ` Rafael J. Wysocki
2020-08-06 12:03     ` Rafael J. Wysocki
2020-08-10  0:44       ` Srinivas Pandruvada
2020-08-11  0:51       ` Francisco Jerez
2020-08-11 15:33         ` Rafael J. Wysocki
2020-08-17 21:06       ` Doug Smythies
2020-09-07  0:16         ` Doug Smythies

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=ff21e71060b589219c21b46b5e26b6c3aca9f951.camel@linux.intel.com \
    --to=srinivas.pandruvada@linux.intel.com \
    --cc=dsmythies@telus.net \
    --cc=francisco.jerez.plata@intel.com \
    --cc=ggherdovich@suse.cz \
    --cc=linux-doc@vger.kernel.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-pm@vger.kernel.org \
    --cc=peterz@infradead.org \
    --cc=rafael@kernel.org \
    --cc=rjw@rjwysocki.net \
    --cc=viresh.kumar@linaro.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).