From: Bob Pearson <rpearsonhpe@gmail.com>
To: jgg@nvidia.com, zyjzyj2000@gmail.com, linux-rdma@vger.kernel.org
Cc: Bob Pearson <rpearsonhpe@gmail.com>
Subject: [PATCH for-next 07/13] RDMA/rxe: Add XRC opcodes to rxe_opcode_info
Date: Thu, 29 Jul 2021 17:49:10 -0500 [thread overview]
Message-ID: <20210729224915.38986-8-rpearsonhpe@gmail.com> (raw)
In-Reply-To: <20210729224915.38986-1-rpearsonhpe@gmail.com>
Add XRC opcodes to rxe_opcode_info.
Signed-off-by: Bob Pearson <rpearsonhpe@gmail.com>
---
drivers/infiniband/sw/rxe/rxe_opcode.c | 328 +++++++++++++++++++++++++
1 file changed, 328 insertions(+)
diff --git a/drivers/infiniband/sw/rxe/rxe_opcode.c b/drivers/infiniband/sw/rxe/rxe_opcode.c
index da719abc1846..af8e05bc63b2 100644
--- a/drivers/infiniband/sw/rxe/rxe_opcode.c
+++ b/drivers/infiniband/sw/rxe/rxe_opcode.c
@@ -949,4 +949,332 @@ struct rxe_opcode_info rxe_opcode[RXE_NUM_OPCODE] = {
}
},
+ /* XRC */
+ [IB_OPCODE_XRC_SEND_FIRST] = {
+ .name = "IB_OPCODE_XRC_SEND_FIRST",
+ .mask = RXE_XRCETH_MASK | RXE_PAYLOAD_MASK | RXE_REQ_MASK
+ | RXE_RWR_MASK | RXE_SEND_MASK | RXE_START_MASK,
+ .length = RXE_BTH_BYTES + RXE_XRCETH_BYTES,
+ .offset = {
+ [RXE_BTH] = 0,
+ [RXE_XRCETH] = RXE_BTH_BYTES,
+ [RXE_PAYLOAD] = RXE_BTH_BYTES
+ + RXE_XRCETH_BYTES,
+ }
+ },
+ [IB_OPCODE_XRC_SEND_MIDDLE] = {
+ .name = "IB_OPCODE_XRC_SEND_MIDDLE]",
+ .mask = RXE_XRCETH_MASK | RXE_PAYLOAD_MASK | RXE_REQ_MASK
+ | RXE_SEND_MASK | RXE_MIDDLE_MASK,
+ .length = RXE_BTH_BYTES + RXE_XRCETH_BYTES,
+ .offset = {
+ [RXE_BTH] = 0,
+ [RXE_XRCETH] = RXE_BTH_BYTES,
+ [RXE_PAYLOAD] = RXE_BTH_BYTES
+ + RXE_XRCETH_BYTES,
+ }
+ },
+ [IB_OPCODE_XRC_SEND_LAST] = {
+ .name = "IB_OPCODE_XRC_SEND_LAST",
+ .mask = RXE_XRCETH_MASK | RXE_PAYLOAD_MASK | RXE_REQ_MASK
+ | RXE_COMP_MASK | RXE_SEND_MASK | RXE_END_MASK,
+ .length = RXE_BTH_BYTES + RXE_XRCETH_BYTES,
+ .offset = {
+ [RXE_BTH] = 0,
+ [RXE_XRCETH] = RXE_BTH_BYTES,
+ [RXE_PAYLOAD] = RXE_BTH_BYTES
+ + RXE_XRCETH_BYTES,
+ }
+ },
+ [IB_OPCODE_XRC_SEND_LAST_WITH_IMMEDIATE] = {
+ .name = "IB_OPCODE_XRC_SEND_LAST_WITH_IMMEDIATE",
+ .mask = RXE_XRCETH_MASK | RXE_IMMDT_MASK | RXE_PAYLOAD_MASK
+ | RXE_REQ_MASK | RXE_COMP_MASK | RXE_SEND_MASK
+ | RXE_END_MASK,
+ .length = RXE_BTH_BYTES + RXE_XRCETH_BYTES + RXE_IMMDT_BYTES,
+ .offset = {
+ [RXE_BTH] = 0,
+ [RXE_XRCETH] = RXE_BTH_BYTES,
+ [RXE_IMMDT] = RXE_BTH_BYTES
+ + RXE_XRCETH_BYTES,
+ [RXE_PAYLOAD] = RXE_BTH_BYTES
+ + RXE_XRCETH_BYTES
+ + RXE_IMMDT_BYTES,
+ }
+ },
+ [IB_OPCODE_XRC_SEND_ONLY] = {
+ .name = "IB_OPCODE_XRC_SEND_ONLY",
+ .mask = RXE_XRCETH_MASK | RXE_PAYLOAD_MASK | RXE_REQ_MASK
+ | RXE_COMP_MASK | RXE_RWR_MASK | RXE_SEND_MASK
+ | RXE_START_MASK | RXE_END_MASK,
+ .length = RXE_BTH_BYTES + RXE_XRCETH_BYTES,
+ .offset = {
+ [RXE_BTH] = 0,
+ [RXE_XRCETH] = RXE_BTH_BYTES,
+ [RXE_PAYLOAD] = RXE_BTH_BYTES
+ + RXE_XRCETH_BYTES,
+ }
+ },
+ [IB_OPCODE_XRC_SEND_ONLY_WITH_IMMEDIATE] = {
+ .name = "IB_OPCODE_XRC_SEND_ONLY_WITH_IMMEDIATE",
+ .mask = RXE_XRCETH_MASK | RXE_IMMDT_MASK | RXE_PAYLOAD_MASK
+ | RXE_REQ_MASK | RXE_COMP_MASK | RXE_RWR_MASK
+ | RXE_SEND_MASK | RXE_START_MASK | RXE_END_MASK,
+ .length = RXE_BTH_BYTES + RXE_XRCETH_BYTES + RXE_IMMDT_BYTES,
+ .offset = {
+ [RXE_BTH] = 0,
+ [RXE_XRCETH] = RXE_BTH_BYTES,
+ [RXE_IMMDT] = RXE_BTH_BYTES
+ + RXE_XRCETH_BYTES,
+ [RXE_PAYLOAD] = RXE_BTH_BYTES
+ + RXE_XRCETH_BYTES
+ + RXE_IMMDT_BYTES,
+ }
+ },
+ [IB_OPCODE_XRC_RDMA_WRITE_FIRST] = {
+ .name = "IB_OPCODE_XRC_RDMA_WRITE_FIRST",
+ .mask = RXE_XRCETH_MASK | RXE_RETH_MASK | RXE_PAYLOAD_MASK
+ | RXE_REQ_MASK | RXE_WRITE_MASK
+ | RXE_START_MASK,
+ .length = RXE_BTH_BYTES + RXE_XRCETH_BYTES + RXE_RETH_BYTES,
+ .offset = {
+ [RXE_BTH] = 0,
+ [RXE_XRCETH] = RXE_BTH_BYTES,
+ [RXE_RETH] = RXE_BTH_BYTES
+ + RXE_XRCETH_BYTES,
+ [RXE_PAYLOAD] = RXE_BTH_BYTES
+ + RXE_XRCETH_BYTES
+ + RXE_RETH_BYTES,
+ }
+ },
+ [IB_OPCODE_XRC_RDMA_WRITE_MIDDLE] = {
+ .name = "IB_OPCODE_XRC_RDMA_WRITE_MIDDLE",
+ .mask = RXE_XRCETH_MASK | RXE_PAYLOAD_MASK | RXE_REQ_MASK
+ | RXE_WRITE_MASK | RXE_MIDDLE_MASK,
+ .length = RXE_BTH_BYTES + RXE_XRCETH_BYTES,
+ .offset = {
+ [RXE_BTH] = 0,
+ [RXE_XRCETH] = RXE_BTH_BYTES,
+ [RXE_PAYLOAD] = RXE_BTH_BYTES
+ + RXE_XRCETH_BYTES,
+ }
+ },
+ [IB_OPCODE_XRC_RDMA_WRITE_LAST] = {
+ .name = "IB_OPCODE_XRC_RDMA_WRITE_LAST",
+ .mask = RXE_XRCETH_MASK | RXE_PAYLOAD_MASK | RXE_REQ_MASK
+ | RXE_WRITE_MASK | RXE_END_MASK,
+ .length = RXE_BTH_BYTES + RXE_XRCETH_BYTES,
+ .offset = {
+ [RXE_BTH] = 0,
+ [RXE_XRCETH] = RXE_BTH_BYTES,
+ [RXE_PAYLOAD] = RXE_BTH_BYTES
+ + RXE_XRCETH_BYTES,
+ }
+ },
+ [IB_OPCODE_XRC_RDMA_WRITE_LAST_WITH_IMMEDIATE] = {
+ .name = "IB_OPCODE_XRC_RDMA_WRITE_LAST_WITH_IMMEDIATE",
+ .mask = RXE_XRCETH_MASK | RXE_IMMDT_MASK | RXE_PAYLOAD_MASK
+ | RXE_REQ_MASK | RXE_WRITE_MASK | RXE_COMP_MASK
+ | RXE_RWR_MASK | RXE_END_MASK,
+ .length = RXE_BTH_BYTES + RXE_XRCETH_BYTES + RXE_IMMDT_BYTES,
+ .offset = {
+ [RXE_BTH] = 0,
+ [RXE_XRCETH] = RXE_BTH_BYTES,
+ [RXE_IMMDT] = RXE_BTH_BYTES
+ + RXE_XRCETH_BYTES,
+ [RXE_PAYLOAD] = RXE_BTH_BYTES
+ + RXE_XRCETH_BYTES
+ + RXE_IMMDT_BYTES,
+ }
+ },
+ [IB_OPCODE_XRC_RDMA_WRITE_ONLY] = {
+ .name = "IB_OPCODE_XRC_RDMA_WRITE_ONLY",
+ .mask = RXE_XRCETH_MASK | RXE_RETH_MASK | RXE_PAYLOAD_MASK
+ | RXE_REQ_MASK | RXE_WRITE_MASK | RXE_START_MASK
+ | RXE_END_MASK,
+ .length = RXE_BTH_BYTES + RXE_XRCETH_BYTES + RXE_RETH_BYTES,
+ .offset = {
+ [RXE_BTH] = 0,
+ [RXE_XRCETH] = RXE_BTH_BYTES,
+ [RXE_RETH] = RXE_BTH_BYTES
+ + RXE_XRCETH_BYTES,
+ [RXE_PAYLOAD] = RXE_BTH_BYTES
+ + RXE_XRCETH_BYTES
+ + RXE_RETH_BYTES,
+ }
+ },
+ [IB_OPCODE_XRC_RDMA_WRITE_ONLY_WITH_IMMEDIATE] = {
+ .name = "IB_OPCODE_XRC_RDMA_WRITE_ONLY_WITH_IMMEDIATE",
+ .mask = RXE_XRCETH_MASK | RXE_RETH_MASK | RXE_IMMDT_MASK
+ | RXE_PAYLOAD_MASK | RXE_REQ_MASK
+ | RXE_WRITE_MASK | RXE_COMP_MASK | RXE_RWR_MASK
+ | RXE_START_MASK | RXE_END_MASK,
+ .length = RXE_BTH_BYTES + RXE_XRCETH_BYTES + RXE_RETH_BYTES
+ + RXE_IMMDT_BYTES,
+ .offset = {
+ [RXE_BTH] = 0,
+ [RXE_XRCETH] = RXE_BTH_BYTES,
+ [RXE_RETH] = RXE_BTH_BYTES
+ + RXE_XRCETH_BYTES,
+ [RXE_IMMDT] = RXE_BTH_BYTES
+ + RXE_XRCETH_BYTES
+ + RXE_RETH_BYTES,
+ [RXE_PAYLOAD] = RXE_BTH_BYTES
+ + RXE_XRCETH_BYTES
+ + RXE_RETH_BYTES
+ + RXE_IMMDT_BYTES,
+ }
+ },
+ [IB_OPCODE_XRC_RDMA_READ_REQUEST] = {
+ .name = "IB_OPCODE_XRC_RDMA_READ_REQUEST",
+ .mask = RXE_XRCETH_MASK | RXE_RETH_MASK | RXE_REQ_MASK
+ | RXE_READ_MASK | RXE_START_MASK | RXE_END_MASK,
+ .length = RXE_BTH_BYTES + RXE_XRCETH_BYTES + RXE_RETH_BYTES,
+ .offset = {
+ [RXE_BTH] = 0,
+ [RXE_XRCETH] = RXE_BTH_BYTES,
+ [RXE_RETH] = RXE_BTH_BYTES
+ + RXE_XRCETH_BYTES,
+ [RXE_PAYLOAD] = RXE_BTH_BYTES
+ + RXE_XRCETH_BYTES
+ + RXE_RETH_BYTES,
+ }
+ },
+ [IB_OPCODE_XRC_RDMA_READ_RESPONSE_FIRST] = {
+ .name = "IB_OPCODE_XRC_RDMA_READ_RESPONSE_FIRST",
+ .mask = RXE_AETH_MASK | RXE_PAYLOAD_MASK | RXE_ACK_MASK
+ | RXE_START_MASK,
+ .length = RXE_BTH_BYTES + RXE_AETH_BYTES,
+ .offset = {
+ [RXE_BTH] = 0,
+ [RXE_AETH] = RXE_BTH_BYTES,
+ [RXE_PAYLOAD] = RXE_BTH_BYTES
+ + RXE_AETH_BYTES,
+ }
+ },
+ [IB_OPCODE_XRC_RDMA_READ_RESPONSE_MIDDLE] = {
+ .name = "IB_OPCODE_XRC_RDMA_READ_RESPONSE_MIDDLE",
+ .mask = RXE_PAYLOAD_MASK | RXE_ACK_MASK | RXE_MIDDLE_MASK,
+ .length = RXE_BTH_BYTES,
+ .offset = {
+ [RXE_BTH] = 0,
+ [RXE_PAYLOAD] = RXE_BTH_BYTES,
+ }
+ },
+ [IB_OPCODE_XRC_RDMA_READ_RESPONSE_LAST] = {
+ .name = "IB_OPCODE_XRC_RDMA_READ_RESPONSE_LAST",
+ .mask = RXE_AETH_MASK | RXE_PAYLOAD_MASK | RXE_ACK_MASK
+ | RXE_END_MASK,
+ .length = RXE_BTH_BYTES + RXE_AETH_BYTES,
+ .offset = {
+ [RXE_BTH] = 0,
+ [RXE_AETH] = RXE_BTH_BYTES,
+ [RXE_PAYLOAD] = RXE_BTH_BYTES
+ + RXE_AETH_BYTES,
+ }
+ },
+ [IB_OPCODE_XRC_RDMA_READ_RESPONSE_ONLY] = {
+ .name = "IB_OPCODE_XRC_RDMA_READ_RESPONSE_ONLY",
+ .mask = RXE_AETH_MASK | RXE_PAYLOAD_MASK | RXE_ACK_MASK
+ | RXE_START_MASK | RXE_END_MASK,
+ .length = RXE_BTH_BYTES + RXE_AETH_BYTES,
+ .offset = {
+ [RXE_BTH] = 0,
+ [RXE_AETH] = RXE_BTH_BYTES,
+ [RXE_PAYLOAD] = RXE_BTH_BYTES
+ + RXE_AETH_BYTES,
+ }
+ },
+ [IB_OPCODE_XRC_ACKNOWLEDGE] = {
+ .name = "IB_OPCODE_XRC_ACKNOWLEDGE",
+ .mask = RXE_AETH_MASK | RXE_ACK_MASK | RXE_START_MASK
+ | RXE_END_MASK,
+ .length = RXE_BTH_BYTES + RXE_AETH_BYTES,
+ .offset = {
+ [RXE_BTH] = 0,
+ [RXE_AETH] = RXE_BTH_BYTES,
+ [RXE_PAYLOAD] = RXE_BTH_BYTES
+ + RXE_AETH_BYTES,
+ }
+ },
+ [IB_OPCODE_XRC_ATOMIC_ACKNOWLEDGE] = {
+ .name = "IB_OPCODE_XRC_ATOMIC_ACKNOWLEDGE",
+ .mask = RXE_AETH_MASK | RXE_ATMACK_MASK | RXE_ACK_MASK
+ | RXE_START_MASK | RXE_END_MASK,
+ .length = RXE_BTH_BYTES + RXE_ATMACK_BYTES + RXE_AETH_BYTES,
+ .offset = {
+ [RXE_BTH] = 0,
+ [RXE_AETH] = RXE_BTH_BYTES,
+ [RXE_ATMACK] = RXE_BTH_BYTES
+ + RXE_AETH_BYTES,
+ [RXE_PAYLOAD] = RXE_BTH_BYTES
+ + RXE_ATMACK_BYTES + RXE_AETH_BYTES,
+ }
+ },
+ [IB_OPCODE_XRC_COMPARE_SWAP] = {
+ .name = "IB_OPCODE_XRC_COMPARE_SWAP",
+ .mask = RXE_XRCETH_MASK | RXE_ATMETH_MASK | RXE_REQ_MASK
+ | RXE_ATOMIC_MASK | RXE_START_MASK
+ | RXE_END_MASK,
+ .length = RXE_BTH_BYTES + RXE_XRCETH_BYTES + RXE_ATMETH_BYTES,
+ .offset = {
+ [RXE_BTH] = 0,
+ [RXE_XRCETH] = RXE_BTH_BYTES,
+ [RXE_ATMETH] = RXE_BTH_BYTES
+ + RXE_XRCETH_BYTES
+ + RXE_XRCETH_BYTES,
+ [RXE_PAYLOAD] = RXE_BTH_BYTES
+ + RXE_XRCETH_BYTES
+ + RXE_ATMETH_BYTES,
+ }
+ },
+ [IB_OPCODE_XRC_FETCH_ADD] = {
+ .name = "IB_OPCODE_XRC_FETCH_ADD",
+ .mask = RXE_XRCETH_MASK | RXE_ATMETH_MASK | RXE_REQ_MASK
+ | RXE_ATOMIC_MASK | RXE_START_MASK
+ | RXE_END_MASK,
+ .length = RXE_BTH_BYTES + RXE_XRCETH_BYTES + RXE_ATMETH_BYTES,
+ .offset = {
+ [RXE_BTH] = 0,
+ [RXE_XRCETH] = RXE_BTH_BYTES,
+ [RXE_ATMETH] = RXE_BTH_BYTES
+ + RXE_XRCETH_BYTES
+ + RXE_XRCETH_BYTES,
+ [RXE_PAYLOAD] = RXE_BTH_BYTES
+ + RXE_XRCETH_BYTES
+ + RXE_ATMETH_BYTES,
+ }
+ },
+ [IB_OPCODE_XRC_SEND_LAST_WITH_INVALIDATE] = {
+ .name = "IB_OPCODE_XRC_SEND_LAST_WITH_INVALIDATE",
+ .mask = RXE_XRCETH_MASK | RXE_IETH_MASK | RXE_PAYLOAD_MASK
+ | RXE_REQ_MASK | RXE_COMP_MASK | RXE_SEND_MASK
+ | RXE_END_MASK,
+ .length = RXE_BTH_BYTES + RXE_XRCETH_BYTES + RXE_IETH_BYTES,
+ .offset = {
+ [RXE_BTH] = 0,
+ [RXE_XRCETH] = RXE_BTH_BYTES,
+ [RXE_IETH] = RXE_BTH_BYTES
+ + RXE_XRCETH_BYTES,
+ [RXE_PAYLOAD] = RXE_BTH_BYTES
+ + RXE_XRCETH_BYTES
+ + RXE_IETH_BYTES,
+ }
+ },
+ [IB_OPCODE_XRC_SEND_ONLY_WITH_INVALIDATE] = {
+ .name = "IB_OPCODE_XRC_SEND_ONLY_INV",
+ .mask = RXE_XRCETH_MASK | RXE_IETH_MASK | RXE_PAYLOAD_MASK
+ | RXE_REQ_MASK | RXE_COMP_MASK | RXE_RWR_MASK
+ | RXE_SEND_MASK | RXE_END_MASK | RXE_START_MASK,
+ .length = RXE_BTH_BYTES + RXE_XRCETH_BYTES + RXE_IETH_BYTES,
+ .offset = {
+ [RXE_BTH] = 0,
+ [RXE_XRCETH] = RXE_BTH_BYTES,
+ [RXE_IETH] = RXE_BTH_BYTES
+ + RXE_XRCETH_BYTES,
+ [RXE_PAYLOAD] = RXE_BTH_BYTES
+ + RXE_XRCETH_BYTES
+ + RXE_IETH_BYTES,
+ }
+ },
};
--
2.30.2
next prev parent reply other threads:[~2021-07-29 22:50 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-29 22:49 [PATCH for-next 00/13] RDMA:rxe: Implement XRC for rxe Bob Pearson
2021-07-29 22:49 ` [PATCH for-next 01/13] RDMA/rxe: Decouple rxe_pkt_info from sk_buff Bob Pearson
2021-08-27 13:01 ` Jason Gunthorpe
2021-07-29 22:49 ` [PATCH for-next 02/13] IB/core: Add xrc opcodes to ib_pack.h Bob Pearson
2021-07-29 22:49 ` [PATCH for-next 03/13] RDMA/rxe: Extend rxe_send_wr to support xrceth Bob Pearson
2021-07-29 22:49 ` [PATCH for-next 04/13] RDMA/rxe: Extend rxe_opcode.h to support xrc Bob Pearson
2021-07-29 22:49 ` [PATCH for-next 05/13] RDMA/rxe: Add XRC ETH to rxe_hdr.h Bob Pearson
2021-07-29 22:49 ` [PATCH for-next 06/13] RDMA/rxe: Add XRC QP type to rxe_wr_opcode_info Bob Pearson
2021-07-29 22:49 ` Bob Pearson [this message]
2021-07-29 22:49 ` [PATCH for-next 08/13] RDMA/rxe: Support alloc/dealloc xrcd Bob Pearson
2021-07-29 22:49 ` [PATCH for-next 09/13] RDMA/rxe: Extend SRQs to support extensions Bob Pearson
2021-07-29 22:49 ` [PATCH for-next 10/13] RDMA/rxe: Compute next opcode for XRC Bob Pearson
2021-07-29 22:49 ` [PATCH for-next 11/13] RDMA/rxe: Extend rxe_verbs and rxe_qp to support XRC Bob Pearson
2021-07-29 22:49 ` [PATCH for-next 12/13] RDMA/rxe: Extend rxe send XRC packets Bob Pearson
2021-07-29 22:49 ` [PATCH for-next 13/13] RDMA/rxe: Enable receiving " Bob Pearson
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