From: Geert Uytterhoeven <geert+renesas@glider.be>
To: Thomas Gleixner <tglx@linutronix.de>,
Jason Cooper <jason@lakedaemon.net>,
Marc Zyngier <marc.zyngier@arm.com>,
Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Simon Horman <horms@verge.net.au>,
Magnus Damm <magnus.damm@gmail.com>,
Chris Brandt <chris.brandt@renesas.com>
Cc: devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org,
linux-kernel@vger.kernel.org,
Geert Uytterhoeven <geert+renesas@glider.be>
Subject: [PATCH v3 4/5] ARM: dts: r7s72100: Add IRQC device node
Date: Thu, 2 May 2019 14:32:19 +0200 [thread overview]
Message-ID: <20190502123220.3016-5-geert+renesas@glider.be> (raw)
In-Reply-To: <20190502123220.3016-1-geert+renesas@glider.be>
Enable support for the IRQC on RZ/A1H, which is a small front-end to the
GIC. This allows to use up to 8 external interrupts with configurable
sense select.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
---
v3:
- Use interrupt-map (+ #address-cells and interrupt-map-mask) instead
of renesas,gic-spi-base,
v2:
- Add Reviewed-by,
- Add "renesas,gic-spi-base".
---
arch/arm/boot/dts/r7s72100.dtsi | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi
index 2211f88ede2ad351..d03dcd919d6f5cfb 100644
--- a/arch/arm/boot/dts/r7s72100.dtsi
+++ b/arch/arm/boot/dts/r7s72100.dtsi
@@ -670,6 +670,25 @@
status = "disabled";
};
+ irqc: interrupt-controller@fcfef800 {
+ compatible = "renesas,r7s72100-irqc",
+ "renesas,rza1-irqc";
+ #interrupt-cells = <2>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0xfcfef800 0x6>;
+ interrupt-map =
+ <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+ <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <7 0>;
+ };
+
mtu2: timer@fcff0000 {
compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";
reg = <0xfcff0000 0x400>;
--
2.17.1
next prev parent reply other threads:[~2019-05-02 12:32 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-02 12:32 [PATCH v3 0/5] ARM: rskrza1: Add RZ/A1 IRQC and input switches Geert Uytterhoeven
2019-05-02 12:32 ` [PATCH v3 1/5] dt-bindings: interrupt-controller: Add Renesas RZ/A1 Interrupt Controller Geert Uytterhoeven
2019-05-07 13:51 ` Simon Horman
2019-05-13 12:17 ` Simon Horman
2019-05-13 17:20 ` Rob Herring
2019-12-11 15:32 ` Geert Uytterhoeven
2019-05-02 12:32 ` [PATCH v3 2/5] irqchip: Add Renesas RZ/A1 Interrupt Controller driver Geert Uytterhoeven
2019-05-07 13:53 ` Simon Horman
2019-05-02 12:32 ` [PATCH v3 3/5] soc: renesas: Enable RZ/A1 IRQC on RZ/A1H and RZ/A2M Geert Uytterhoeven
2019-06-06 8:37 ` Simon Horman
2019-05-02 12:32 ` Geert Uytterhoeven [this message]
2019-05-20 11:27 ` [PATCH v3 4/5] ARM: dts: r7s72100: Add IRQC device node Simon Horman
2019-05-02 12:32 ` [PATCH v3 5/5] ARM: dts: rskrza1: Add input switches Geert Uytterhoeven
2019-05-20 11:29 ` Simon Horman
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