From: Atish Patra <atish.patra@wdc.com>
To: linux-kernel@vger.kernel.org
Cc: Mark Rutland <mark.rutland@arm.com>,
devicetree@vger.kernel.org,
Damien Le Moal <Damien.LeMoal@wdc.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Dmitriy Cherkasov <dmitriy@oss-tech.org>,
Anup Patel <anup@brainfault.org>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
Atish Patra <atish.patra@wdc.com>,
Rob Herring <robh+dt@kernel.org>,
Palmer Dabbelt <palmer@sifive.com>,
linux-riscv@lists.infradead.org,
Thomas Gleixner <tglx@linutronix.de>
Subject: [PATCH 3/4] RISC-V: Remove per cpu clocksource
Date: Mon, 3 Dec 2018 12:57:30 -0800 [thread overview]
Message-ID: <1543870651-16669-4-git-send-email-atish.patra@wdc.com> (raw)
In-Reply-To: <1543870651-16669-1-git-send-email-atish.patra@wdc.com>
There is only one clocksource in RISC-V. The boot cpu initializes
that clocksource. No need to keep a percpu data structure.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
---
drivers/clocksource/riscv_timer.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/clocksource/riscv_timer.c b/drivers/clocksource/riscv_timer.c
index 96af7058..39de6e49 100644
--- a/drivers/clocksource/riscv_timer.c
+++ b/drivers/clocksource/riscv_timer.c
@@ -49,7 +49,7 @@ static unsigned long long riscv_clocksource_rdtime(struct clocksource *cs)
return get_cycles64();
}
-static DEFINE_PER_CPU(struct clocksource, riscv_clocksource) = {
+static struct clocksource riscv_clocksource = {
.name = "riscv_clocksource",
.rating = 300,
.mask = CLOCKSOURCE_MASK(BITS_PER_LONG),
@@ -106,7 +106,6 @@ static long __init riscv_timebase_frequency(struct device_node *node)
static int __init riscv_timer_init_dt(struct device_node *n)
{
int cpuid, hartid, error;
- struct clocksource *cs;
hartid = riscv_of_processor_hartid(n);
cpuid = riscv_hartid_to_cpuid(hartid);
@@ -116,8 +115,7 @@ static int __init riscv_timer_init_dt(struct device_node *n)
/* This should be called only for boot cpu */
riscv_timebase = riscv_timebase_frequency(n);
- cs = per_cpu_ptr(&riscv_clocksource, cpuid);
- clocksource_register_hz(cs, riscv_timebase);
+ clocksource_register_hz(&riscv_clocksource, riscv_timebase);
error = cpuhp_setup_state(CPUHP_AP_RISCV_TIMER_STARTING,
"clockevents/riscv/timer:starting",
--
2.7.4
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next prev parent reply other threads:[~2018-12-03 20:57 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-12-03 20:57 [PATCH 0/4] Timer code cleanup Atish Patra
2018-12-03 20:57 ` [PATCH 1/4] dt-bindings: Correct RISC-V's timebase-frequency Atish Patra
2018-12-07 16:29 ` Palmer Dabbelt
2018-12-03 20:57 ` [PATCH 2/4] RISC-V: Support per-hart timebase-frequency Atish Patra
2018-12-07 16:42 ` Palmer Dabbelt
2018-12-07 23:36 ` Atish Patra
2018-12-03 20:57 ` Atish Patra [this message]
2018-12-07 17:00 ` [PATCH 3/4] RISC-V: Remove per cpu clocksource Palmer Dabbelt
2018-12-03 20:57 ` [PATCH 4/4] RISC-V: Fix non-smp kernel boot on SMP systems Atish Patra
2018-12-07 17:00 ` Palmer Dabbelt
2018-12-07 23:31 ` Atish Patra
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