From: Yash Shah <yash.shah@sifive.com>
To: robh+dt@kernel.org, mark.rutland@arm.com, paul.walmsley@sifive.com
Cc: devicetree@vger.kernel.org, aou@eecs.berkeley.edu,
atish.patra@wdc.com, gregkh@linuxfoundation.org,
linux-kernel@vger.kernel.org, alexios.zavras@intel.com,
Yash Shah <yash.shah@sifive.com>,
palmer@dabbelt.com, tglx@linutronix.de, bmeng.cn@gmail.com,
linux-riscv@lists.infradead.org, allison@lohutok.net
Subject: [PATCH 1/2] riscv: dts: Add DT support for SiFive L2 cache controller
Date: Mon, 9 Dec 2019 16:55:05 +0530 [thread overview]
Message-ID: <1575890706-36162-2-git-send-email-yash.shah@sifive.com> (raw)
In-Reply-To: <1575890706-36162-1-git-send-email-yash.shah@sifive.com>
Add the L2 cache controller DT node in SiFive FU540 soc-specific DT file
Signed-off-by: Yash Shah <yash.shah@sifive.com>
---
arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
index afa43c7..812db02 100644
--- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
+++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
@@ -19,6 +19,16 @@
chosen {
};
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ l2_lim: lim@0x8000000 {
+ reg = <0x0 0x8000000 0x0 0x2000000>;
+ };
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -54,6 +64,7 @@
reg = <1>;
riscv,isa = "rv64imafdc";
tlb-split;
+ next-level-cache = <&l2cache>;
cpu1_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
@@ -77,6 +88,7 @@
reg = <2>;
riscv,isa = "rv64imafdc";
tlb-split;
+ next-level-cache = <&l2cache>;
cpu2_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
@@ -100,6 +112,7 @@
reg = <3>;
riscv,isa = "rv64imafdc";
tlb-split;
+ next-level-cache = <&l2cache>;
cpu3_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
@@ -123,6 +136,7 @@
reg = <4>;
riscv,isa = "rv64imafdc";
tlb-split;
+ next-level-cache = <&l2cache>;
cpu4_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
@@ -246,6 +260,18 @@
#pwm-cells = <3>;
status = "disabled";
};
+ l2cache: cache-controller@2010000 {
+ compatible = "sifive,fu540-c000-ccache", "cache";
+ cache-block-size = <64>;
+ cache-level = <2>;
+ cache-sets = <1024>;
+ cache-size = <2097152>;
+ cache-unified;
+ interrupt-parent = <&plic0>;
+ interrupts = <1 2 3>;
+ reg = <0x0 0x2010000 0x0 0x1000>;
+ memory-region = <&l2_lim>;
+ };
};
};
--
2.7.4
next prev parent reply other threads:[~2019-12-09 11:25 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-12-09 11:25 [PATCH 0/2] L2 ccache DT and cacheinfo support to read no. of L2 cache ways enabled Yash Shah
2019-12-09 11:25 ` Yash Shah [this message]
2019-12-09 11:25 ` [PATCH 2/2] riscv: cacheinfo: Add support to determine no. of L2 cache way enabled Yash Shah
2019-12-14 2:12 ` Palmer Dabbelt
2019-12-15 19:56 ` Paul Walmsley
2019-12-23 8:53 ` Yash Shah
2019-12-14 2:13 ` [PATCH 1/2] riscv: dts: Add DT support for SiFive L2 cache controller Palmer Dabbelt
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