From: Yash Shah <yash.shah@sifive.com>
To: linus.walleij@linaro.org, bgolaszewski@baylibre.com,
robh+dt@kernel.org, mark.rutland@arm.com, palmer@dabbelt.com,
paul.walmsley@sifive.com
Cc: devicetree@vger.kernel.org, aou@eecs.berkeley.edu,
jason@lakedaemon.net, linux-gpio@vger.kernel.org, maz@kernel.org,
linux-kernel@vger.kernel.org, atish.patra@wdc.com,
Yash Shah <yash.shah@sifive.com>,
sagar.kadam@sifive.com, tglx@linutronix.de, bmeng.cn@gmail.com,
linux-riscv@lists.infradead.org, sachin.ghadi@sifive.com
Subject: [PATCH v4 6/6] riscv: dts: Add DT support for SiFive FU540 GPIO driver
Date: Tue, 10 Dec 2019 16:41:14 +0530 [thread overview]
Message-ID: <1575976274-13487-7-git-send-email-yash.shah@sifive.com> (raw)
In-Reply-To: <1575976274-13487-1-git-send-email-yash.shah@sifive.com>
Add the gpio DT node in SiFive FU540 soc-specific DT file.
Enable the gpio node in HiFive Unleashed board-specific DT file.
Signed-off-by: Yash Shah <yash.shah@sifive.com>
---
arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 15 ++++++++++++++-
arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts | 4 ++++
2 files changed, 18 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
index afa43c7..96dca93 100644
--- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
+++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
@@ -246,6 +246,19 @@
#pwm-cells = <3>;
status = "disabled";
};
-
+ gpio: gpio@10060000 {
+ compatible = "sifive,fu540-c000-gpio", "sifive,gpio0";
+ interrupt-parent = <&plic0>;
+ interrupts = <7>, <8>, <9>, <10>, <11>, <12>, <13>,
+ <14>, <15>, <16>, <17>, <18>, <19>, <20>,
+ <21>, <22>;
+ reg = <0x0 0x10060000 0x0 0x1000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&prci PRCI_CLK_TLCLK>;
+ status = "disabled";
+ };
};
};
diff --git a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
index 88cfcb9..609198c 100644
--- a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
+++ b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
@@ -94,3 +94,7 @@
&pwm1 {
status = "okay";
};
+
+&gpio {
+ status = "okay";
+};
--
2.7.4
next prev parent reply other threads:[~2019-12-10 11:12 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-12-10 11:11 [PATCH v4 0/6] GPIO & Hierarchy IRQ support for HiFive Unleashed Yash Shah
2019-12-10 11:11 ` [PATCH v4 1/6] genirq: introduce irq_domain_translate_onecell Yash Shah
2019-12-10 11:11 ` [PATCH v4 2/6] irqchip: nvic: Use irq_domain_translate_onecell instead of custom func Yash Shah
2019-12-10 11:11 ` [PATCH v4 3/6] irqchip: sifive: Support hierarchy irq domain Yash Shah
2019-12-10 11:11 ` [PATCH v4 4/6] gpio: sifive: Add DT documentation for SiFive GPIO Yash Shah
2019-12-18 20:51 ` Rob Herring
2019-12-10 11:11 ` [PATCH v4 5/6] gpio: sifive: Add GPIO driver for SiFive SoCs Yash Shah
2019-12-10 11:11 ` Yash Shah [this message]
2020-01-20 9:09 ` [PATCH v4 0/6] GPIO & Hierarchy IRQ support for HiFive Unleashed Marc Zyngier
2020-01-21 8:53 ` Yash Shah
2020-01-29 15:00 ` Palmer Dabbelt
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