From: Chen Wang <unicornxw@gmail.com>
To: aou@eecs.berkeley.edu, chao.wei@sophgo.com, conor@kernel.org,
krzysztof.kozlowski+dt@linaro.org, palmer@dabbelt.com,
paul.walmsley@sifive.com, robh+dt@kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-riscv@lists.infradead.org, haijiao.liu@sophgo.com,
xiaoguang.xing@sophgo.com, guoren@kernel.org, jszhang@kernel.org,
inochiama@outlook.com
Cc: Chen Wang <unicorn_wang@outlook.com>
Subject: [PATCH 4/4] riscv: dts: add resets property for uart node
Date: Tue, 9 Jan 2024 17:17:51 +0800 [thread overview]
Message-ID: <18e1093a7f1357af7d9e9df12ede2e99725632e3.1704790558.git.unicorn_wang@outlook.com> (raw)
In-Reply-To: <cover.1704790558.git.unicorn_wang@outlook.com>
From: Chen Wang <unicorn_wang@outlook.com>
Add resets property for uart0 for completeness, although it is
deasserted by default.
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
---
arch/riscv/boot/dts/sophgo/sg2042.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
index f59081d4f0ee..03266f216021 100644
--- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi
+++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
@@ -327,6 +327,7 @@ uart0: serial@7040000000 {
clock-frequency = <500000000>;
reg-shift = <2>;
reg-io-width = <4>;
+ resets = <&rstgen RST_UART0>;
status = "disabled";
};
};
--
2.25.1
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prev parent reply other threads:[~2024-01-09 9:18 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-09 9:16 [PATCH 0/4] riscv: sophgo: add reset support for SG2042 Chen Wang
2024-01-09 9:16 ` [PATCH 1/4] dt-bindings: reset: sophgo: support SG2042 Chen Wang
2024-01-09 15:19 ` Krzysztof Kozlowski
2024-01-10 0:06 ` Chen Wang
2024-01-09 9:17 ` [PATCH 2/4] reset: sophgo: add SG2042 reset generator driver Chen Wang
2024-01-09 9:17 ` [PATCH 3/4] riscv: dts: add reset generator for Sophgo SG2042 SoC Chen Wang
2024-01-09 9:17 ` Chen Wang [this message]
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