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From: Johan Hovold <johan@kernel.org>
To: Paul Walmsley <paul.walmsley@sifive.com>
Cc: Mark Rutland <mark.rutland@arm.com>,
	devicetree@vger.kernel.org, Paul Walmsley <paul@pwsan.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Palmer Dabbelt <palmer@sifive.com>,
	linux-kernel@vger.kernel.org, Rob Herring <robh+dt@kernel.org>,
	linux-riscv@lists.infradead.org
Subject: Re: [PATCH 5/7] riscv: dts: add initial support for the SiFive FU540-C000 SoC
Date: Mon, 21 Jan 2019 15:10:40 +0100	[thread overview]
Message-ID: <20190121141040.GM3691@localhost> (raw)
In-Reply-To: <20181215052154.24347-6-paul.walmsley@sifive.com>

On Fri, Dec 14, 2018 at 09:21:52PM -0800, Paul Walmsley wrote:
> Add initial support for the SiFive FU540-C000 SoC.  This is a 28nm SoC
> based around the SiFive U54-MC core complex and a TileLink
> interconnect.
> 
> This file is expected to grow considerably as more device drivers are
> added to the kernel.
> 
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Palmer Dabbelt <palmer@sifive.com>
> Cc: Albert Ou <aou@eecs.berkeley.edu>
> Cc: devicetree@vger.kernel.org
> Cc: linux-riscv@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org
> Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
> Signed-off-by: Paul Walmsley <paul@pwsan.com>
> ---
>  arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 182 +++++++++++++++++++++
>  1 file changed, 182 insertions(+)
>  create mode 100644 arch/riscv/boot/dts/sifive/fu540-c000.dtsi
> 
> diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
> new file mode 100644
> index 000000000000..0ef314cf17b6
> --- /dev/null
> +++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi

> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		timebase-frequency = <1000000>;
> +		cpu0: cpu@0 {
> +			clock-frequency = <0>;
> +			compatible = "sifive,e51", "sifive,rocket0";

Looks like you forgot the currently required "riscv" compatible here and
below.

But perhaps it's the binding and arch code that should be revised
instead (e.g. as per your discussion with Rob elsewhere in this thread).

Johan

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  parent reply	other threads:[~2019-01-21 14:10 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-12-15  5:21 [PATCH 0/7] arch: riscv: add DT file support, starting with the SiFive HiFive-U Paul Walmsley
2018-12-15  5:21 ` [PATCH 1/7] arch: riscv: add support for building DTB files from DT source data Paul Walmsley
2018-12-15  5:21 ` [PATCH 2/7] dt-bindings: riscv: sifive: add documentation for the SiFive FU540 Paul Walmsley
2018-12-20 20:57   ` Rob Herring
2018-12-15  5:21 ` [PATCH 3/7] dt-bindings: riscv: cpus: add E51 cores to the list of documented CPUs Paul Walmsley
2018-12-20 21:01   ` Rob Herring
2019-01-04 22:46     ` Palmer Dabbelt
2019-01-05  1:10       ` Rob Herring
2018-12-15  5:21 ` [PATCH 4/7] dt-bindings: riscv: cpus: add U54 " Paul Walmsley
2018-12-15  5:21 ` [PATCH 5/7] riscv: dts: add initial support for the SiFive FU540-C000 SoC Paul Walmsley
2018-12-16  3:12   ` kbuild test robot
2019-01-21 14:10   ` Johan Hovold [this message]
2018-12-15  5:21 ` [PATCH 6/7] dt-binding: riscv: sifive: add documentation for FU540-based boards Paul Walmsley
2018-12-20 21:04   ` Rob Herring
2018-12-15  5:21 ` [PATCH 7/7] riscv: dts: add initial board data for the SiFive HiFive Unleashed Paul Walmsley
2018-12-20 21:31   ` Rob Herring
2019-04-06 23:14     ` Paul Walmsley
2018-12-16 23:35 ` [PATCH 0/7] arch: riscv: add DT file support, starting with the SiFive HiFive-U Paul Walmsley

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